.probe or.print
Syntax
.probe [tran] [name1 = ]ov1 [[name2 = ]ov2] ... [[namen = ]ovn] [depth = value] [subckt = name] net=[name] [exclude = pn1] [exclude = pn2] ... [preserve=all|port|none]
Description
In Spectre FX, .print is automatically converted to .probe. These statements are used to probe node voltages, device currents, and port currents. The statements can contain hierarchical names and wildcards for nodes, ports, or elements, and can be embedded within the scope of a subcircuit.
The statements also support the following:
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Multiple statements in the netlist file
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Output variables in different formats
Arguments
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tran
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Defines the analysis type as transient. This is an optional parameter and can be skipped because Spectre FX supports only transient analysis.
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ov1 ov2....ovn
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Name of the output variable (it can be the node voltage, branch current, port current, Verilog-A instance port voltage, or Verilog-A instance internal variable value).
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v(node_name) probes the node_name voltage. node_name can be hierarchical and can contain question marks and wildcards. For example: v(x?1.*.n*). -
i(element_name) probes the branch current output through the element element_name. element_name can be hierarchical and can contain question marks and wildcards. For example: i(x?1.*.n*). -
v1(element_name) probes the voltage of the first terminal for the element element_name, v2 probes the voltage of the second terminal, v3 probes the voltage of the third terminal, and v4 probes the voltage of the fourth terminal (useful when the node name of a terminal is unknown). -
x(instance_port_name)returns the current flowing into the subcircuit port, including all lower hierarchical subcircuit ports. It can be used to probe the power and ground ports of an instance, even if the ports are defined as global nodes and do not appear in the subcircuit port list. The instance_port_name can be hierarchical and can contain question marks and wildcards. For example: x(x?1.*.n*.vdd). -
vol = v(node1, node2) probes the voltage difference between node1 and node2 and assigns the result to the variable vol. -
expr = par('expression') probes the expression of simple output variables and assigns the result to expr. The expression can contain variables and also all the mathematical operators and built-in or user-defined functions. An expression can also contain the names of other expressions. -
var_name(veriloga_instance) probes the var_name voltage for veriloga_instance. var_name can be either a port name or an internal variable name of a Verilog-A module. veriloga_instance is the instance name of a Verilog-A module, which can be hierarchical and can contain question marks and wildcards. For example: PD(IO.AN?.B*).
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all(veriloga_instance)probes all the port voltages and internal variable values for veriloga_instance. veriloga_instance can be hierarchical and can contain question marks and wildcards. For example: all(IO.AN?.B*).
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depth=value
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Specifies the depth in the circuit hierarchy that a wildcard name applies to. If it is set as 1, only the nodes at the current level are applied (default value is infinity). This parameter has an alias level. The option probe_level decides how to count the hierarchical depth.
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subckt=name
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Specifies the subcircuit to which this statement applies to. By default, it applies to the top level. If the statement is already in a subcircuit definition, this parameter is ignored. Setting this parameter is equivalent to defining the statement within a subcircuit declaration. Wildcards are supported.
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exclude
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Specifies the output variables to be excluded from the probe. The names can be node or element names and can contain wildcards. This parameter has an alias except.
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preserve
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Defines the content of the nodes probed with wildcard scoping. Possible values are:
none: Probes all the nodes and ports connected to active devices (default). Nodes connected only to passive elements are not probed.
all: Probes all nodes, including the nodes connected to passive elements, and probes all ports.
port: Probes only the ports in subcircuits.
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Examples
.probe v(n1) i1(m1) vdiff = v(n2,n3) expr1 = par('v(n1)+2*v(n2)')
Tells the Spectre FX simulator to probe the voltage at node n1 and the current i1 for element M1. The voltage difference between nodes n2 and n3 is probed and assigned to vdiff. In addition, an expression of voltages at nodes n1 and n2 is probed and assigned to expr1.
.probe tran v(*) i(r1) depth = 2 subckt = VCO
Tells the Spectre FX simulator to probe the voltages for all the nodes in the subcircuit named VCO and one level below in the circuit hierarchy. The current of the resistor r1 is also probed for all the instances of the subcircuit VCO. The reported names of r1 are appended with the circuit call path from the top level to VCO. This is equivalent to the situation where the statement .probe tran v(*) i(r1) depth = 2 is written in the subcircuit definition of VCO in the netlist file.
.probe tran x(xtop1.block1.in)
Tells the Spectre FX simulator to report the current of port in for instance block1, which is instantiated at the top-level block xtop.
.print tran x(xtop.*)
Tells the Spectre FX simulator to probe the current of ports for instance xtop and all instances below.
.probe tran v(*) subckt=VCO preserve=all
Probes the voltages for all nodes in VCO, including port names and internal nodes that are only connected to resistors and capacitors.
.probe tran v(*) exclude=net* exclude=bl* depth=2
Probes all node voltages of the top level and one hierarchy below, except for the voltages of nodes matching the pattern net* and bl*.
.probe tran v1(x1.x3.mp1) v2(x3.xp.mp4)
Probes the drain of x1.x3.mp1 and gate of x3.xp.mp4.
.probe tran out(IO.ANA.VREG) ps3(IO.ANA.VREG) all(IO.ANA.C*)
Probes the voltage of port out and the value of the internal variable ps3 for the Verilog-A instance IO.ANA.VREG, as well as all the port voltages and internal variable values for Verilog-A instances that match the name IO.ANA.C*.
Related Topics
.lprobe or .lprint
save
.measure
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