Convergence Difficulties (convergence)

Description

If you are having convergence difficulties, try the following suggestions:

1. Evaluate and resolve any notice, warning, or error messages.
2. Ensure that the topology checker is being used (set topcheck=full on options statement) and heed any warnings it generates.
3. Perform sanity check on the parameter values by using the parameter range checker (use +param param-limits-file as a command line argument) and heed any warnings. Print the minimum and maximum parameter value by using info analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.
4. Small floating resistors connected to high impedance nodes can cause convergence difficulties. Avoid small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
5. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
6. Increase the value of gmin (on options statement).
7. Loosen tolerances, particularly absolute tolerances like iabstol (on options statement). If tolerances are set too tight, they might preclude convergence.
8. Try to simplify the nonlinear component models to avoid regions that might contribute to convergence problems in the model.

DC Convergence Suggestions

After you have a solution, write it to a nodeset file by using the write parameter, and read it back in on subsequent simulations by using the readns parameter.

1. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file, and set as many nodes as possible.
2. If convergence difficulties occur when using nodesets or initial conditions, try increasing rforce (on options statement).
3. If this is not the first analysis and the solution from the previous analysis is far from the solution for this analysis, set restart=yes.
4. If simulating a bipolar analog circuit, ensure that the region parameter on all transistors and diodes is set correctly.
5. If the analysis fails at an extreme temperature, but succeeds at room temperature, try adding a DC analysis that sweeps temperature. Start at room temperature, sweep to the extreme temperature, and write the final solution to a nodeset file.
6. Use numeric pivoting in the sparse matrix factorization by setting pivotdc=yes (on options statement). Sometimes, it is also necessary to increase the pivot threshold to a value in the range of 0.1 to 0.5 by using pivrel (on options statement).
7. Divide the circuit into smaller pieces and simulate them individually. However, ensure that the results are close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
8. Check the connections to ground. Convergence problems might result if there are no connections to ground.
9. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is cheap when none of the signals in the circuit are changing) and write the final point to a nodeset file. To make transient analysis more efficient, set the integration method to backward Euler (method=euler) and loosen the local truncation error criteria by increasing lteratio, say to 50. Occasionally, this approach fails, or is slow because the circuit contains an oscillator. Often, for finding the dc solution, the oscillation can be eliminated by setting the minimum capacitance from each node to ground (cmin) to a large value.

Transient Convergence Suggestions

1. Ensure that a complete set of parasitic capacitors is used on nonlinear devices to avoid jumps in the solution waveforms. On MOS models, specify nonzero source and drain areas.
2. Use the cmin parameter to install a small capacitor from every node in the circuit to ground. This usually eliminates any jump in the solution.

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