Routing Assistant User Interface for Standard Cell

The Routing Assistant has the following components:

Routing Assistant Toolbar	Lets you access the buttons to complete the steps of the routing flow.
Routing Assistant Tabs	Lets you specify the options for running the selected routing type.
Routing Assistant Command Buttons	Lets you access the buttons on each tab to compete a routing task.

Routing Assistant Toolbar

The following table lists the functions of the different buttons on the Routing assistant toolbar:

Icon	Command	Description
	Change routing mode	Selects the routing mode. The two routing modes are Automatic and Interactive.
	Change routing type	Changes the type of routing you want to run on the design. The three routing types are: Device, StdCell, Chip Assembly.
	Raise the pre-routing browser	Provides net information prior to routing.
	Set router constraints	Opens the Routing Constraint Manager.
	Load preset options	Lets you load options from an existing preset file.
	Save preset options	Lets you save the Routing Assistant options to a file.
	Delete preset options	Lets you delete an existing preset file.

Routing Assistant Tabs

The following table lists the functions of the different tabs in the Routing assistant:

Tab	Description
Setup	Lets you specify the settings for running the router.
Check	Lets you select the checks that you want to run before routing the design.
Supply	Lets you run the power router. You need to have power and ground wireType tracks in your width spacing patterns. Usually, you run this routing before placement.
Route	Lets you specify the scope of signal routing.
Results	Lets you select the scope and the results column that should be displayed in Routing Results Browser.

The options in the Routing Assistant depend on the routing type in which the design is open. The three routing types are:

Device-level flow helps users become familiar with the device-level placement and routing solution in Virtuoso for advanced nodes, with the focus on uniform designs.
Standard Cell routing technology seamlessly integrates the NanoRoute™ router in the Virtuoso environment. It provides different ways for you to generate WSPs as well as route without them, relying on Innovus-created tracks.
Chip Assembly routing technology targets top-level designs that have macro instances, I/O pads, and can also contain standard cell areas. It also addresses memory type designs using spine routing.

Setup

The following table describes the fields available on the Setup tab of the Routing assistant for standard cell routing.

Field	Description
*Options*	Lets you setup some general options for standard cell routing.
Check DRCs after routing	Automatically runs DRD design rule checks before routing. Environment variable: setup_checkDRCsAfterRouting
Lock Colors after routing	Locks colored shapes for routing. This option is set based on the technology file layer rules. If the process has trim shapes that cut only locked color shapes, than the option is selected by default and editable. However, if the process has no trim shapes, the option is deselected by default and not editable. If, trim shapes work on locked and unlocked shapes, the option is selected by default and editable. Environment variable: setup_lockColorsAfterRouting
Process setup	Selects the process node to be used for routing.
*Layer Settings*	Lets you specify the layers for which to generate WSPs.
Routing Layers	Specifies valid bottom and top routing layers. The bottom and top layer fields contain both frontside layers and backside layers as defined in the technology file. When a backside layer is specified in the bottom and top layer fields, the standard cell Nano Router is unable to run. As a result, the routing process is aborted and an error message is displayed in CIW.
Wire Types Map	Displays a form with a table that maps the wireType to the symbol to be used in the pattern specification in the table.
Wire Types Assign to nets	Displays a form with a table that assigns wireTypes to nets.
*Layer table*	Provides a list of layers on which WSPs are generated.
Layer	The name of the layer.
Pattern	Generates the pattern of WSP as per your requirement. For example, `gs3ns2g3` where `g` stands for ground, `s` for signal, `n` for Null, `p` for power, and so on.
Dir	The routing direction of the layer. The supported routing directions include Horizontal, Vertical, Orthogonal, and Forbid. Forbid implies that no direction is considered.
W	The width specified for the layer.
S	The spacing specified for the layer.
WSP	The width spacing patterns defined for the layer.

Check

The following table describes the fields available on the Check tab of the Routing assistant for standard cell routing.

Field	Description
*Check*	Provides a list of various checks that can be run for the routing type.
Select	Lets you specify the checks to be run. Click All or None to select or deselect all checks with a single click.
*Technology setup*	Lets you specify the checks related to the technology setup.
R-MSOA PDK in tech graph	Checks that there is a R-MSOA library in the technology graph.
Design ITDB check	Checks if the design library has an incremental technology database (ITDB) library that references a Rapid MSOA PDK.
*Abstract data*	Lets you specify the checks related to abstract data in the design.
Abstract & layout views available	Checks for availability of abstract and layout views for standard cell instances.
Abstract & layout pins match	Checks that all pins match between layout and abstract views for standard cell instances.
*Design interoperability*	Lets you specify the design interoperability checks between Innovus and Virtuoso.
Net sigTypes specified	Checks that signal nets at level 0 are not connected to power and ground nets at level 1.
Net sigTypes consistency	Checks that there is a power and ground sigType net in the layout.
Existing wiring in route object	Checks for pre-existing wires in the routing objects.
Existing wiring compatible	Checks for the incompatible wires and wire segments. It also checks the name of standard via variants. If the via variant name is invalid, a message is displayed for the invalid name in CIW.
Pins on routing layers	Checks whether there are pins on non-routing layers in the design.
Complete NDR specification	Checks for the completeness of constraint group non-default rules (NDR), such as valid layers, spacing values, and so on.
Custom constraints compatible	Checks the compatibility of custom constraints.
Rows interoperable	Checks the row interoperability to ensure that each active row has a siteDef.
WSPs interoperable	Checks for the interoperability of active WSPs of each layer.
Pins conform to active WSPs	Checks for the conformance of pins to active WSPs.
Bus terms order & interface bit	Checks bus annotation and reports any bus terminals (`busTerms`) that do not have ordering (`busOrder`) information. It also checks the status of interface bits.
VLS XL compliant	Checks whether or not the design is XL compliant. This means that the connectivity is XL compliant so that hierarchy is set up correctly between terms and instTerms throughout the design hierarchy.
Express pcell cache	Checks for the presence of a Pcell cache.
*Routability*	Lets you specify the routability checks.
Existing DRCs	Specifies whether to run design rule checks using DRD. Environment variable: check_existingDRCs
Objects outside PR boundary	Lets you check for the objects that are outside the PR boundary.
Blocked pins	Lets you check if there are any blocked pins in the design.
*Output*	Settings to display the output of routing checks.
Display Log	Controls the display of the checker log in the CIW once the checks are run. Environment variable: check_displayLog
Overwrite last log	Controls the overwriting of the last log file. When the option is deselected, the existing log file is retained. Environment variable: check_overwriteLog, checkerLogDir
Markers	Controls the generation of markers for errors. These error markers can be viewed in the Misc tab of the Annotation Browser. Environment variable: check_generateMarkers

Supply

The following table describes the fields available on the Supply tab of the Routing assistant for standard cell routing.

Field	Description
*Scope*	Defines the scope of supply routing.
Supply Nets	Specifies whether to route all or selected supply nets. Environment variable: supply_nets
Within	Specifies whether to route everything inside the PR boundary or only within a guard ring or figGroup, or specify an area. You can also create supply stripes inside a row region or wsp region. The available options are: PR boundary, Guardring/FigGroup, Area, and WSP/Row. Environment variable: supply_netsWithin
*Options*	Lets you specify the options for supply routing.
Only use layers with WSP P/G tracks	Provides a list of layers in the Supply stripes cyclic field for bottom and top layers that have power or ground tracks in the active WSP for that layer. Environment variable: supply_useExisitingPGTracks
Supply stripes	Specifies the top and bottom layers of the supply stripes layer range that pins should be created on.
Generate supply stripes	Generates stripes when supply routing is run. Environment variable: supply_genSupplyStripes
Insert vias for supply stripes	Inserts the vias between the intersection of the layer above and below the via. Environment variable: supply_insertVias
Connect to overlapped terminals	Specifies whether or not the supply router should connect to IO pins and guard rings. Environment variable: supply_connectToTerminals
Insert trim to fix DRCs	Inserts trims between the intersection of the layer above and below the via in the supply grid to fix DRC errors. Environment variable: supply_insertTrim
Share tracks for supply nets	Distinguishes upper and below areas for one WSP track by instance’s pin name. Environment variable: supply_shareTracks
Create supply grid as a group	Creates the supply grid as a figGroup. Environment variable: supply_createGridAsGroup
Ignore boundary tracks	Ignores generating stripes on tracks that are on the PR boundary. Environment variable: supply_IgnoreBoundaryTracks
Ignore boundary vias	Ignores generating vias on tracks that are on the PR boundary. Environment variable: supply_IgnoreBoundaryVias
Assign to nets	Opens a form with a table that assigns wireTypes to nets.
Pull-back	Controls the spacing of power nets per layer from the PR boundary to avoid any DRC violation.
*Pins*	Lets you specify the supply routing options for pins in the design.
Create	Creates a pin instead of a pathSeg for the supply stripe. Environment variable: supply_createPins
Create label	Creates labels on pins when the Pins Create option is selected in the Supply tab of the Routing assistant. Environment variable: supply_createPinLabel
Use all supply stripe layers	Creates pins on the layers on which stripes are generated. Environment variable: supply_pinLayerSet
Use selected layers	Creates pins on only the layers that are selected. Environment variable: supply_pinLayerSet
Create on ends	Creates pins on the ends of stripes instead of one long pin when the Pins Create option is selected. Environment variable: supply_createPinsOnEnds
Create on pin purpose	Lets you use a pin as the layer purpose for the created pin. Environment variable: supply_createPinsOnPinPurpose
*Update*	Lets you select the supply routing options to be deleted.
Delete Supply stripes	Deletes the stripes generated by the supply router before power routing. Environment variable: supply_deleteStripes
Delete Supply vias	Deletes the vias generated by the supply router before power routing. Environment variable: supply_deleteVias
*Output*	Lets you specify the settings to display the routing results.
Current cellview	Write the output of the supply routing to the current cellview. Environment variable: supply_defaultRoutedView, supply_routedLOC
Other cellview	Lets you select a view name to write the output of the supply routing to another cellview. You can also specify a non-database existing name. The name of the cell is `$cell_proute` with `_proute` as the postfix to the cell name. The view name is always `layout`. Environment variable: supply_defaultRoutedView, supply_routedLOC, supply_defaultRoutedCellExpression
Save routing only	Specifies whether to copy only the supply grid or all initial data and the supply grid to the new cellview. Environment variable: supply_saveRoutingOnly

Route

The following table describes the fields available on the Route tab of the Routing assistant for standard cell routing type.

Field	Description
*Scope*	Defines the scope of signal routing.
Nets	Specifies whether you want to route all nets, selected nets, or nets with opens or shorts. Environment variable: route_nets
Include Supply Nets	Specifies whether to route power and ground (`tieHi` and `tieLo`) nets. Environment variable: route_supplyNets
Within	Specifies whether to route everything inside the PR boundary or area. Environment variable: route_netsWithin
*Options*	Lets you specify the options for signal routing.
Update pins	Controls whether the placement and snapping of IO pins will be done in Innovus. Environment variable: route_updatePins
Snap to closest same edge track	Snaps the IO pin to the closest track on the same layer and same edge. Environment variable: route_updatePinOption
Snap to any edge	Snaps the IO pin to snap to any edge on any layer within the specified layer range. Environment variable: route_updatePinOption
Allowed layer range	Specifies the layer range on which to snap the IO pin to any edge.
Create routing as a group	Specifies whether or not to create routing as a figGroup. Environment variable: route_createRoutingAsAGroup
Fix post-route DRC errors	Resolves existing shorts and spacing violations by removing violating routes and repairing connectivity on the target nets. Environment variable: route_fixPostRouteDRCErrors
*Update*	Lets you select the signal routing options to be deleted.
Delete Wires and vias	Deletes the wires, vias, and shield lines created by the router. Environment variable: route_deleteWiresAndVias
Delete Manual routing	Deletes the pre-routed wires and vias that are created manually. Environment variable: route_deletePreroutes
*Output*
Display log	Controls the display of the Innovus routing log when signal routing is run. Environment variable: route_displayLog
Overview last log	Specifies whether to overwrite the last log or keep the existing one. When the option is selected, the existing log is overwritten. Environment variable: route_createRoutingAsAGroup
Current cellview	Write the output of the supply routing to the current cellview. Environment variable: route_routedLOC, route_defaultRoutedView
Other cellview	Lets you specify a view name to write the output of the signal routing to another cellview. Environment variable: route_routedLOC, route_defaultRoutedView
Save routing only	Specifies whether or not to save standard cell routing settings. Environment variable: route_saveRoutingOnly

Results

The following table describes the fields available on the Results tab of the Routing assistant for standard cell routing type.

Field	Description
*Scope*	Defines the scope of the routing results.
Nets	Specifies whether you want to show the routing result of all nets, selected nets, or only nets with opens. Environment variable: results_nets
Include supply Nets	Shows the routing result of power and ground nets. Environment variable: results_supplyNets
Within	Shows the routing result of nets inside the PR boundary or within an area. When the option is selected as Area, the available icons are: Set area bbox to visible area : Sets the visible area of the design canvas as the region. Draw the area bbox : Lets you draw the region on the design canvas. Use show/hide the area bbox to display or hide the highlight around the region. Environment variable: results_netsWithin
*Summary of latest run*	Displays the summary of the routing results for various parameters, such as Time, Instances, Nets, DRCs, Opens, Shorts, Wire Length, Vias.
*Output*	Specifies the output columns to be displayed in the Routing Results Browser
Select	Lets you select either all or none parameters for which output should be displayed. The parameters are: Rule Violations, Symmetry Violations, Matched Length Violations, Shield Violations, Opens, Shorts, DRCs, Wirelength, Vias, Ratio, Pin count, Manhattan X, and Manhattan Y.

Routing Assistant Command Buttons

The following table lists the functions of the different command buttons on the Routing assistant:

Icon	Command	Description
	Snap pins to WSPs	Snaps IO pins to width spacing patterns.
	Show WSP Manager	Displays WSP Manager.
	Import WSPs	Imports width spacing patterns to the current cellview.
	Auto-generate WSPs	Generates width spacing patterns automatically on the selected layers.
	Run pre-route checks	Runs pre-routing checks and saves the result to a log file.
	Run power route	Runs power routing.
	Run signal router	Runs signal routing.
	Show results browser	Displays the Virtuoso Routing Results Browser.

Virtuoso Automated Standard Cell Placement and Routing Flow Guide
Product Version IC23.1, November 2023