Product Documentation
Virtuoso Design Planning and Analysis User Guide
Product Version IC23.1, November 2023

Pin Accessibility Checker Form

Use the Pin Accessibility Checker form to verify the routability of standard cells.

Field Description

Technology LEF

Specifies the additional technology file settings to be used by the Pin Accessibility checker.

LEF File(s)

Specifies the additional technology file to be honored.

Environment variable: vfpPACLefFiles

Browse

Opens the Navigator assistant to select the required technology file.By default, the standard cell technology definitions are honored. In certain situations, for example, when standard cells are instantiated in a design that has different technology definitions, you can use LEF File(s) to load the additional technology file to be honored.

Load

Loads the specified LEF file. Technology definitions from the selected file are added to the current layout library technology data. The new combined technology file is attached to the current library. As a result, a combined list including vias and via rules is generated.

Design Information

Specifies the LCV that contains the standard cells and the directory in which all temporary files are to be stored.

Lib(s)

Specifies the standard cell libraries that contain the required standard cells.

Cell(s)

Specifies the required standard cells on which the tool is to be run.

View(s)

Specifies the view to be created by the tool.

Output Directory

Specifies the directory in which all temporary files and views are to be stored.

The directory contains the following information:

  • The selected standard cells.
  • The standard cell extended pin views created by the Pin Accessibility Checker. Multiple output views are generated for the specified topology, utilization, and metal layer. The view names have a suffix that represents the postfix. For example *_topBottom and *_leftRight represent the topology, *_60 represents the utilization, and *_M3 represents the routing top layer. The postfix helps identify the topology, utilization, and top-layer combination used to generate the extended pin views. These views are then passed on to Innovus for routing.
  • The routed view created by Innovus. Innovus uses the standard cell extended pins view as the input, runs the router, and generates a routed view.

Environment variable: vfpPACOutputDir

Placement Topology

Specifies the routing plan for the design.

Select

Specifies the placement topology for the standard cells. The available values are:

  • Left_Right: Places the same cell six times with the R0 and MY orientations.
  • Top_Bottom: Places the same cell three times with the R0, R180, and MY orientations.

Environment variables: vfpPACPlacementTopology, vfpPACLeftRightTopology, vfpPACTopBottomTopology

Utilization%

Specifies the area to be used for routing.

Snap to Grid

Specifies the routing metal layer grid on which the cells are to be snapped. This ensures that the lower left point of the cell's PR boundary lies on the appropriate metal layer grid. By default, the routing grid of the top metal layer is selected for snapping cells.

Environment variable: vfpPACSnapToGridLyr

Add Via on PG Rail

Specifies whether vias are to be generated on the power or ground rails. Select a value from the list.

Rail Width

Specifies the width of rails in the layout view. For example, you can make the width greater than the one drawn in the layout. If no value is specified or if the specified value is less than the minimum width, then rail width is the same as the width of the underlying metal shape.

Environment variable: vfpPACCustomRailWidth

Router Options

Specifies the routing preferences for the Innovus router.

Routing Layers

Specifies the highest routing layer to be used.

Layer Width/Spacing

Specifies the width and spacing values for each routing layer. Click Define to open the Layer Width Spacing constraint table in a new window. After making changes, close the window to populate values in the Layer Width/Spacing field.

Voltage

Switches on high voltage rule-based routing for input designs with voltage spacing rules defined in the technology file. Select this option to ensure that the voltage spacing rules for the selected voltage are honored during routing in high-voltage cells.

Critical Net

Specifies the nets that are to be routed first.

Double Cut Vias

Inserts double-cut vias in critical nets.

Run Router

Routes the topology view for each standard cell instance by running Innovus in the background without checking out an Innovus license.

Environment variable: vfpPACEnableRouter

Check Violations in Router

Opens the Innovus router graphical user interface and generates violation markers that can be viewed in the Innovus violation browser. This option requires a Cadence Innovus router license.

When deselected, the routed views are opened using Virtuoso and the violation markers are generated in the Annotation Browser assistant.

Environment variable: vfpPACCheckViolationsInRouter

Related Topics

Running the Pin Accessibility Checker


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