Results of Accelerating the Design Import Process
Speed for design import for the netlist view has been increased.
Example 1: A sample system specification for which the speedup results were observed are as follows:
Manufacturer :Sun (Sun Microsystems)
System Model :Ultra 5/10
Main Memory :128 MB
Virtual Memory :268MB
Number of CPUs :1
CPU Type :sparc
OS Name :SunOS
OS Version :5.5.1
Kernel Version :SunOS Release 5.5.1 Version Generic_105428-01
[UNIX(R) System V Release 4.0]
|
The acceleration results for both the original and new time without pre-compiled libraries for netlist view are as follows:
|
No of Modules
|
Size of Design
|
Previous time (sec)
|
New Time (sec)
|
Speedup factor
|
|
4
|
872K
|
3044
|
369
|
8.25
|
|
47
|
970K
|
2288
|
397
|
5.76
|
|
21
|
90K
|
260
|
237
|
1.09
|
|
371
|
3.32M
|
1924
|
1251
|
1.54
|
|
1073
|
3.04M
|
3294
|
2510
|
1.31
|
|
1
|
6.06M
|
25175
|
652
|
38.61
|
Example 2: Another sample system specification for which the speedup results were observed are as follows:
Manufacturer :Sun (Sun Microsystems)
System Model :Ultra 60
Main Memory :1024 MB
Virtual Memory :1.0 GB
Number of CPUs :2
CPU Type :sparc
OS Name :SunOS
OS Version :5.5.1
Kernel Version :SunOS Release 5.5.1 Version Generic_103640-12
[UNIX(R) System V Release 4.0]
|
The acceleration results for both the original and new time with pre-compiled libraries for netlist view are as follows:
|
No. of modules in design
|
2391
|
13
|
9
|
|
No. of modules referenced from Verilog libraries
|
112/407
|
54/446
|
70/830
|
|
Size of Design
|
25M
|
4.69M
|
2.7M
|
|
Combined Size of Verilog libraries
|
1.4M
|
33K
|
1.4M
|
|
Previous time with -v option
|
1:55:02.5
|
1:01:29.0
|
1:10:49.4
|
|
New time with -v option
|
1:05:49.1
|
5:17.1
|
3:30.6
|
|
Speedup Factor
|
1.75
|
11.63
|
20.18
|
|
New time with pre-compiled library
|
54:21.7
|
5:07.8
|
1:17.1
|
|
Speedup Factor
|
2.12
|
11.99
|
55.12
|
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