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Contents

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1

Introduction to Verilog In

Prerequisites for Using Verilog In

Licensing Requirements

Memory Requirements

Verilog In Design Flow

Starting Verilog In

Importing Data with Verilog In

Saving Import Options in Verilog In

Loading Import Options in Verilog In

Classification of Modules in Verilog In

Behavioral Cell Modules

Structural Cell Modules

Verilog HDL Cell Modules

Guidelines for Design Modification in Verilog In

Guidelines for Creating and Editing Symbols

Significance of Reference Libraries for Importing Incomplete Designs

Escaped Name Mapping in Verilog In

Parameters and Defparams in Verilog In

Exceptions in Data Import by Verilog In

Output Files Created by Verilog In

The verilogIn.log File

The verilogIn.map.table File

2

Verilog In Command-Line Mode

Starting Verilog In in Command-Line Mode

Components of the ihdl Command

The ihdl_files File

Options Specified with -f in the ihdl Command

The ihdl_parameter File

Parameters Specified in the ihdl_parameter File

Customization of Verilog In Defaults Using the .cdsenv File

Verilog In Options and Parameters Specified in the ihdl_parameter File

Net Expression Parameters

3

Verilog In with Verilog 2001 Support

Signed Arithmetic

Sized and Typed Parameters and Local Parameters

Attributes in HDL Source

Inherited Connections

Named Parameter Assignment

ANSI-C Style Port Declarations

Combined Port and Type Declaration

Indexed Part Selects

Power Operator and Arithmetic Shift Operator

A

Verilog In Form

Import Options

Global Net Options

Schematic Generation Options

B

Pre-Compiled Libraries in Verilog In

Creating Pre-Compiled Libraries

Uses of Pre-Compiled Libraries

Guidelines for Using Pre-Compiled Libraries

Limitations of Using Pre-Compiled Libraries in Verilog In

Acceleration of Pre-Compiled Library Creation

Results of Accelerating the Design Import Process

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