Product Documentation
Cadence VHDL-AMS Overview
Product Version 22.09, April 2022

5

Mixed-Signal Value Conversions

The analog extensions of the VHDL-AMS language introduce some complexities not present in a digital only language. Because values in the analog domain are continuous and values in the digital domain are discrete, converting across domains now involves issues of both the translation of values and the timing of the exchange.

In the digital domain, it is the signals and variables that contain dynamic data values. These objects are assigned values in processes and change at discrete times. In the analog domain, the terminals and quantities are the objects containing values. The values of these objects are continuous functions with respect to time. These differences mean that when you model a mixed signal system, you must consider the mechanism for exchanging values between digital and analog.

The method you use to exchange values across domains depends on whether the value is being converted from an analog value to a digital value or from a digital value to an analog value.

Analog to Digital Conversion

You can, from a digital context, sample an analog value at various time points and convert the sampled value to a digital value, or you can monitor an analog value and use the value to trigger an event based on a threshold crossing. The following sections illustrate these approaches.

Sampling Analog Values

You can directly use the value of an analog-valued quantity in an assignment statement of a digital process. For example, the following model of a flip-flop uses a clock to determine when to sample the quantity q. The value of the quantity q then determines the new digital value of out.

library ieee;  use ieee.math_real.all;
library ncvhdl_lib;
ENTITY sampler IS
END sampler;
ARCHITECTURE behavior_sampler OF sampler IS
    signal clk : bit;
    signal output : bit;
    QUANTITY q   : real;
 -- Source constants
 constant thresh : real := 3.4;
 constant amplitude : REAL := 2.0 * thresh;
 constant frequency : REAL := 0.16 * 0.1e9  ;
BEGIN
 clock: process(clk)
 BEGIN
  clk <= not clk after 10 ns;
 END PROCESS clock;
 flipflop: PROCESS (clk) 
 BEGIN
  if (clk = ’1’) then
   if (q > thresh) then
    output <= ’1’;
   else
    output <= ’0’;
   end if;
  end if;
 END PROCESS flipflop; 
 -- sin source
 q == amplitude * sin(2.0 * MATH_PI * frequency * now);
END behavior_sampler;

Using Analog Values to Trigger a Digital Event

You can also use the ’above attribute to trigger a digital event based on analog changes. The expression Q’above(E) represents a boolean-valued signal that is true when the value of Q is greater than the value of the expression E and is false otherwise. You can use the Q’above(E) signal in a process sensitivity list or in a wait statement to trigger the execution of a digital process.

For example, in the following model of an inverter the statement

wait on v_in’above(threshold)

ensures that the value of output changes only when the value of the analog signal crosses the threshold value.

inverter: process is
    constant threshold : real := 2.5;
begin
    if (v_in > threshold) then
     output <= '0';
 else
  output <= '1';
 end if;
 wait on v_in’above(threshold);
end process inverter;

Digital to Analog Conversion

Simultaneous statements can directly access digital signals. For example, if you have a bit-valued signal S and an across quantity Q you can legally use a simultaneous statement like the following:

Q == real(S) * maxval;

Unfortunately, the above statement introduces a discontinuity into quantity Q whenever signal S changes value. As a result, you need to use the S’ramp or S’slew attributes to smooth the transitions. Avoiding discontinuities allows the simulator to run much more efficiently.

For example, the following example converts the digital signal clk to the analog quantity analog_out, and uses the s’ramp attribute to smooth the output.

library ieee;  use ieee.math_real.all;
library ncvhdl_lib;
use ncvhdl_lib.std_decls.all;
entity v_source is
end entity v_source;
architecture behavior of v_source is
    constant maxv : real := 3.5;
    signal rclk : real := 0.0;
    signal clk : bit := ’0’;
    terminal t1: electrical;
    quantity analog_out across analog_curr through t1;
begin
    clock: process is
    begin
     if (clk = ’0’) then
   wait for 3 ns;
   rclk <= maxv;
   clk <= ’1’;
  else
   wait for 3 ns;
   rclk <= 0.0;
   clk <= ’0’;
  end if;
 end process clock;
 analog_out == rclk’ramp(1.0e-9);
end architecture behavior;

Notice, in the following figure, how using the S’ramp attribute results in a ramp, rather than a step function, on the analog_out signal.

Break Statement

Signal or variable changes in a process sometimes cause discontinuities in the analog part of a design. If this happens in your design, you need to ensure that your digital code runs a break statement whenever a process introduces a discontinuity.

There are two types of break statements: concurrent and sequential.

The following example illustrates how to use a concurrent break statement. When the switch turns on or off (that is when sw changes value) the conversion process introduces a discontinuity into the v_out signal. To announce the discontinuity, the concurrent break statement runs whenever there is an event on the signal sw. 

library ieee;  use ieee.math_real.all;
library ncvhdl_lib;
use ncvhdl_lib.std_decls.all;
entity v_source is
end entity v_source;
architecture behavior of v_source is
    signal sw : bit := ’0’;
    quantity v_out : real := 0.0;
begin
    if (sw = ’0’) use
     v_out == 0.0;
 else
  v_out == 5.0;
 end use;
 toggle: process is
 begin
  sw <= not sw after 5 ns;
  wait on sw;
 end process toggle;
 break on sw;
end architecture behavior;

Return to top
 ⠀
X