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Contents

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Preface

Related Documents

Internet Mail Address

Typographic and Syntax Conventions

1

Introduction

What is VHDL-AMS?

Extensions to VHDL

Benefits of VHDL-AMS

Implications of Using VHDL-AMS

References to the VHDL-AMS Language Reference

Using VHDL-AMS with Other Languages

2

VHDL-AMS Modeling Styles

Levels of Abstraction

Analog Abstraction Hierarchy

Conservative Systems

Terminals

Reference Terminal

Reference Directions

Analog Systems

Simultaneous Statements

Conditional Behavior in Simultaneous Statements

Design Hierarchy

Digital Abstraction Hierarchy

System Level

Chip Level

Register Transfer Level

Logic Gate Level

Circuit Level

Mixed-Signal Systems

3

Example: Design Entity

Illustrated Example of an Inverter Model

4

VHDL-AMS Language Elements

Entity and Architecture

Entities

Architectures

Multiple implementations of One Interface

Packages and Libraries

Packages

Libraries

Declarations

Natures

Types

Objects and Interface Objects

Subprograms

Statements

Sequential Statements

Concurrent Statements

Simultaneous Statements

Expressions

Predefined Operators and Operator Precedence

Static and Non- Static Expressions

5

Mixed-Signal Value Conversions

Analog to Digital Conversion

Sampling Analog Values

Using Analog Values to Trigger a Digital Event

Digital to Analog Conversion

Break Statement

A

Standard Packages Supported

IEEE Libraries for VHDL-AMS

IEEE Standard VHDL Mathematical Packages

MATH_REAL

MATH_COMPLEX

B

Reserved Words

C

Advice and Solutions for VHDL-AMS Compiler Issues

Glossary

Index

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