Backtrace Enable Signals of Special Cells

This involves backtracing of the internal net to map the enable or control signals of special cells to the boundary ports. Backtracing is required to get the appropriate functional attribute related to the enable or control signals in the Liberty macro model after detecting the corresponding function of the logic generating the signals.

Liberty registration for standard and special cells in the setup is a mandatory requirement to extract a correct function for the enable or control signals of low power special cells as per the design implementation

The backtracing is supported for following registered configurations:

For buffers, shorts, and inverters, the two-terminal devices with single input and output, such as inverters and buffers, can be backtraced. The polarity of the signal does not change while backtracing through instances, unless the instances are inverter cells. You can register these cells as Inverter. If an instance with more than two terminals is present in the path, backtracing stops and an error message is displayed. Inverter and buffer registration is done as shown below.
```
inverter (
```
```
(nil "stdInv*" nil)
```
```
("gpdk*" "inv*" nil)
```
```
)
```
```
buffer (
```
```
(nil "stdBuf*" nil)
```
```
("gpdk*" "buf*" nil (nil shortedTerminalMap (("p" "q") ("o" "y"))))
```
```
)
```
The terminal map is a mandatory requirement for backtracing when a cell contains multiple input and output and is registered as an inverter or a buffer.
For standard isolation or level-shifter instances, signals are backtraced from output pin to input pins. For power switch instances, the signals are backtraced from the acknowledge pin (buffered enable) to enable the pin of the instance. This lets the backtracing to be performed for the control signals of all the power switch cells to the same macro port resulting in the correct enable and shutoff conditions.
For simple logic gate, the backtracing is done through the special cell enable pin to the output pin of the logic gate that has multiple input pins is supported. All input pins of a logic gate can be backtraced separately to the maximum extent possible.
However, a cell can be registered as LogicGate (simple logic gate) only if it matches any of the following criteria:
- There are no multiple output pins in the cell.
- The boolean function is present in the setup file.
- Only AND, NAND, OR, NOR, and XOR Boolean functions are considered.
The cells are registered as LogicGate devices along with Boolean functions of the cells.
```
logicGate (
```
```
("sample" "or*" nil (nil booleanFunction "OR"))
```
```
("sample" "xor*" nil (nil booleanFunction "XOR"))
```
```
("sample" "and*" nil (nil booleanFunction "AND"))
```
```
("sample" "nand*" nil (nil booleanFunction "NAND"))
```
```
("sample" "inv" nil (nil booleanFunction "NOR"))
```
```
)
```
A custom logic can also be registered with the desired terminal mapping between its output and input ports to be suitably backtraced if it lies in between the enable/control signal and the boundary port generating it. For any block net, all the modules from parent of leaf cell to parent of block net are checked if one or more of these are custom devices. In case, more than one modules are found as custom devices, the top most module is given the priority.
```
  customLogic (
```
```
   ("ALIB" "WiFi" nil (nil relatedTerminalMap "y1=x1&x2,y2=x3|x4,y3=x5^x6"))
```
```
  )
```
```
 )
```
Algorithm Standard Cell
The function of output pins is extracted in terms of input pins by backtracing through transistors or other primitive elements, such as resistors and capacitors. You can use the maxInputPinsForAlgoStdCellABT and maxOutputPinsForAlgoStdCellABT flags while doing logic extraction for any unregistered cells.
Cells registered as transistors
While back tracing through transistors back tracing would stop if the successive channel or gate crossings before continuing back tracing reaches a predefined limit. The maxConsecutiveTxGateCrossingsForABT and maxConsecutiveTxChannelCrossingsForABT flags are utilized while back tracing through transistor logic, either seen in its flat form or seen inside algorithm standard cell. Which back-tracing through the transistors, the back tracing would stop if the successive channel or gate crossings before continuing back tracing reaches a predefined limit.
The user-defined macros and switch functions in internal and regulated nets can be backtraced.
You can print the derivations of switch_function and isolation_enable_condition expressions.
Power Manager also extracts the following user defined attributes:
- switch_function_off:
  - String type user-defined simple attribute for pg_pin group
  - Printed along with a switch_function
  - A boolean expression of macro cell input pins that evaluates to 1 only when output supply is fully OFF.
- isolation_enable_condition_off
  - String type user-defined simple attribute for pin group
  - Printed along with the isolation_enable_condition
  - A boolean expression of macro cell input pins that evaluates to 1 only when the isolation function of a level shifter or isolation cell is fully disabled.
The reporting of automatically identified transfer functions of cells/pins in the backtracing path is also supported.

Virtuoso Power Manager User Guide
Product Version IC23.1, June 2023