Power Intent Verification Requirements

The accurate power intent verification using CLP has the following mandatory requirements before proceeding for preparing and subsequently running CLP.

• cmos_sch, schematic, or Verilog_PG (Non-text) required as stop views for PDK cells (Standard/Special cells).
  • If cmos_sch, schematic, or Verilog_PG (symbol) exists with power and ground pins, they can be consumed as it is.
  
  A Verilog symbol view with the PG information is illustrated below.
  
  
• A netlist control file having flags for specific netlist customizations.
  If you explicitly specify a netlist control file during preparation for running CLP, set the following flags appropriately:
  • To ensure that the power and ground information is correctly captured in the netlist. This is required for correct power intent verification of the design.
    • hnlInhConnUseDefSigName='t
    • vlogifDeclareGlobalNetLocal='t
    • hnlPrintInhConAtTop='t
    • hnlHonorInhConnEscapeName='t
    • hnlVerilogDeclareScalarSig='t
    • simVerilogEnableEscapeNameMapping= 't
    • hnlMapNetInName
    • hnlMapTermInName
  • To ensure that redundant information does not show at the module or instance level in the netlist. For example, information of primitive devices (mos/resistor/capacitors and diodes).
    hnlUserIgnoreCVList
  • For creating the stub view (no module definition) for macro Liberty blocks, just an instance line with power/ground nets that is identified by traversing the schematic.
    hnlUserStubCVList

Related Topics

Virtuoso NC Verilog Environment User Guide

Open Simulation System Reference

Verifying Power Intent of a Design

Checking Design Hierarchy

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