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Contents

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1

About the NC-Verilog Integration Environment

Licensing Requirements

NC-Verilog Integration Tools

Entering the Environment

Entering the Environment from CIW

Entering the Environment from a Schematic View

Main NC-Verilog Window

SimVision Window

SimCompare

Managing the Run Directory

Test Fixture Files

Using Command Line Interface

Queuing Verilog Netlist Processes

2

NC-Verilog Integration Control Commands

About the Main NC-Verilog Window

Status Line

Menu Banner

Fixed Menu

Run Directory

Top Level Design Options

Simulate Options

Commands Menu

Setup Menu

SDF Delay Annotation

Setting the Delay Annotation Options

Netlist

Record Signals

Simulation

Simulation Compare

Cross Selection Setup

Results Menu

Netlist

Job Monitor

Help Menu

Fixed Menu

Customizing Command Form Options

3

Setting Up the Simulation Environment

Simulation Process Flowchart

Selecting a Design

Initializing a Design

Netlisting a Design

Specify Netlisting Options

Run Hierarchical Netlister

Creating Stimulus Template File

4

Running the Simulation

Simulation Process Flowchart

Introduction

Setting SDF Delay Annotation

Setting the Delay Annotation Options

Setting Simulation Setup Options

Simulating a Design

Cross-Selecting Design Objects

Cross-Selecting Objects during Interactive Simulation

Cross-Selecting Objects Using Simulation Data

Cross-Selecting Iterated Instances

Running a Batch Simulation

Monitoring Batch Simulations

Comparing Simulation Results

5

Netlisting

Simulation Process Flowchart

Netlister Inputs and Outputs

Property Types

Verilog Properties

Timing Delays and Drive Strengths

Verilog Views

Netlister Actions

Inherited Connection Support

Features

Limitations

Design Example

Netlist Example

Enhanced Support for Inherited Connections

Using a Verilog File Reference

Iterated Instances Support

Controlling Netlister Actions

Using View Lists

Using Stop Lists

Starting the Netlister

User Messages

Global Nets Not Power or Ground

Synchronizing Terminals

Adding Simulation Properties

Properties Added for Imported Modules

Adding Verilog Properties

Adding Delay Properties

Adding Drive Strength Properties

Adding nlAction Properties

Adding Ancillary Data Files

Netlisting Switch-RC Cells

Setting the RC Data Variable

Entering Switch-RC Properties

Formatting Functions for MOS Cells

Switch-RC Instance Properties

Switch-RC Net Properties

Using CDF Properties

Printing CDF Parameters in Inline Explicit Format

Formatting Netlists

hnlVerilogFormatInst Property

verilogFormatProc Property

Netlisting AutoLayout Views

Customizing Test Fixture Variables

Modifying the Test Module Name

Modifying the Test Fixture Template Name

Saving the Template File

Accessing the Map Table in the Stimulus File

Adding Design Kits to the Test Fixture File

Customizing the Netlisting Variables

Variables for Netlist Setup Form Controls

Other Variables used by Verilog Formatter

File Structure Created by the Netlister

Directories

Files

Split Bus

Support for Verilog IEEE 1364-2001

6

Working with the Stimulus

Simulation Process Flowchart

Specifying the Test Fixture

Using Default Test Fixture Files

Editing an Existing Test Fixture

Working with Test Fixture Files

A

Customizing Your Environment

Customizing Command Form Option Settings

Form Options and SKILL Variables

Specifying an Editor for Text Files

Generating Logical Verilog Netlists of Designs

Overview

Terminology

Generating a Logical Verilog Netlist

Comparison Between a Regular and a Logical Verilog Netlist

B

Running Simulations with Xcelium

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