Minimizing Potential Violations

When constraints are set for your design, design rule checks will flag violations. Some violations can be minimized by setting conditions for routing. For example, a partially overlapping via over a pin shape can result in a minimum edge violation. To prevent this condition during routing, use

setvar droute.vias_must_be_fully_enclosed true

When droute.vias_must_be_fully_enclosed is true, VirtuosoSpace-based Router  only adds vias at pins if the via can be fully enclosed in the pin shape. In addition, to restrict the vias that are affected by the fully enclosed requirement by specifying layers, use

setvar droute.vias_must_be_fully_enclosed_on_layer {layerName…}

Examples:

setvar droute.vias_must_be_fully_enclosed_on_layer {M01 M02}

setvar droute.vias_must_be_fully_enclosed_on_layer {Metal9}

setvar droute.vias_must_be_fully_enclosed_on_layer {} // same as all layers

The droute.vias_must_be_fully_enclosed_on_layer variable is only recognized when droute.vias_must_be_fully_enclosed is true.

Related Topics

Preparing the Routing Environment

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