ATPG Compatible Verilog Netlists

The primary responsibility of engineers is to deliver scan patterns with complete confidence in their accuracy. Automatic Test Pattern Generation (ATPG) tools are used to generate scan patterns. Scan pattern generation as a process requires three inputs: the netlist of the design, ATPG tool configuration files, and the definition of the library cells used.

However, due to limited support for behavioral constructs, usually ATPG tools cannot use Verilog definitions of library cells except Verilog-1995 structural netlists. As a result, the library cells must be defined in a tool-specific language or in a simpler, structural form of Verilog.

Virtuoso SystemVerilog Netlister lets you generate netlists of Verilog text files that are compatible with the ATPG technology. These netlists let you find an input or test sequence in Verilog text files. The ATPG functionality within Virtuoso SystemVerilog Netlister has the following main features:

• All text views must be Verilog constructs. Views created in other languages are not supported.
• All nets are defined as wire in the netlist.
• All parameters of cells or instances are ignored and are not printed in netlist.
• All instance arrays are expanded by default.
• Aliases can be printed using tran statements instead of using cds_alias, cds_thru, or assign statements.
• Generates a single netlist file. This netlist file contains the Verilog modules created from the schematic and the Verilog modules from the text views. Cells with same names from different libraries and different views are generated in a single netlist file with unique names.

Related Topics

Generating ATPG Compatible Verilog Netlists

Verilog Tab

enableVerilogATPG

useTranForCdsAliasThru

vlogCompatVersion

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