Wreal Connections to VHDL real and SystemVerilog real

Wreal signals can be connected to other real type variables, signals, and domains, such as VHDL real, SystemVerilog real, or electrical.

The connection between VHDL real and SystemVerilog real numbers is a direct connection because the data type is equivalent. The following example shows how the different languages can interact with each other. The top-level generates a real value that is passed into two sub-modules, one being a VHDL and the other a SystemVerilog module.

`include "disciplines.vams "

module vhdl_sv_wreal ();

  wreal    real_in;
  wreal    sv_real_out;
  wreal    vhdl_real_out ;

  real real_in_reg;
  sv_sub i_sv_sub (real_in, sv_real_out);
  vhdl_sub i_vhdl_sub (real_in, vhdl_real_out);

initial begin
  real_in_reg = 1.0;
  #10 real_in_reg = 5.0;
  #10 real_in_reg = 3.6;
  #10 $finish;
end // initial begin

always @(real_in) begin
    $display("%M: real_in = %f", real_in);
end
always @(vhdl_real_out) begin
  $display("%M: vhdl_real_out = %f", vhdl_real_out);
end
always @(sv_real_out) begin
  $display("%M: sv_real_out = %f", sv_real_out);
end
assign real_in = real_in_reg;

endmodule

In the example, there is no interface code or any type conversion necessary to the connection. The VHDL sub module is written in pure digital VHDL using the real data type for the ports. The incoming real value is printed out to ensure that we are receiving the right value. After a multiplication by 2.0, the value is transferred to a sub module written in Verilog-AMS/wreal. The output value of the wreal sub module is again printed and multiplied before it is passed back to the top-level module.

library ieee;
use ieee.std_logic_1164.all;
USE STD.textio.all;
use work.all;

entity vhdl_sub is
  port (
    real_in: in real;
    vhdl_real_out : out real
  );
end;

architecture behavioral of vhdl_sub is
signal real_2 : real;
signal real_4 : real;

component wreal_sub
  port (
    wreal_in: in real;
    wreal_out : out real
  );
end component;

BEGIN
  process(real_in)
    variable l : line;
  BEGIN

    write(l, vhdl_sub'path_name);
    write(l, string'(" : real_in = "));
    write(l, real'image(real_in) );
    writeline( output, l );
  end process;

process(real_4)
  variable l : line;
BEGIN

  write(l, vhdl_sub'path_name);
  write(l, string'(" : real_4 = "));
  write(l, real'image(real_4) );
  writeline( output, l );
end process;

i_wreal_sub : wreal_sub
  port map (
    wreal_in => real_2,
    wreal_out => real_4
  );

 real_2 <= real_in * 2.0;
 vhdl_real_out <= real_4 * 2.0;
end;

The following example shows the wreal sub-block. It receives the value, prints it, and returns the double value back to the upper-level module.

`include "disciplines.vams"

module wreal_sub(wreal_in, wreal_out);
   input wreal_in;
   wreal wreal_in;
   output wreal_out;
   wreal wreal_out;

   real wreal_out_reg;

   always @(wreal_in) begin
     wreal_out_reg = wreal_in * 2.0;
     $display("%M: real_in = %f", wreal_in);
   end

   assign wreal_out = wreal_out_reg;
endmodule // wreal_sub

In parallel to the VHDL sub-module, an equivalent SystemVerilog implementation is instantiated. It performs the same operation as described above and instantiates the same sub-level wreal module.

module sv_sub (real_in, sv_real_out);

   input var real real_in;
   output var real sv_real_out;

   var real sv_real_2;
   var real sv_real_4;

   always @(real_in) begin
     sv_real_2 = real_in * 2.0;
     $display("%M: real_in = %f", real_in);
   end

   always @(sv_real_4) begin
     $display("%M: sv_real_4 = %f", sv_real_4);
   end

   wreal_sub i_wreal_sub (sv_real_2, sv_real_4);
   assign sv_real_out = sv_real_4 * 2.0;

endmodule // sv_real

As expected, the output displays the multiplication of the input value in the two sub-level blocks.

xcelium> run
vhdl_sv_wreal:i_vhdl_sub:vhdl_sub : real_4 = 0.0
vhdl_sv_wreal:i_vhdl_sub:vhdl_sub : real_in = 0.0
vhdl_sv_wreal: real_in = 1.000000
vhdl_sv_wreal:i_vhdl_sub:vhdl_sub : real_in = 1.0
vhdl_sv_wreal.i_sv_sub: real_in = 1.000000
vhdl_sv_wreal.i_sv_sub.i_wreal_sub: real_in = 2.000000
vhdl_sv_wreal.i_vhdl_sub:i_wreal_sub: real_in = 2.000000
vhdl_sv_wreal:i_vhdl_sub:vhdl_sub : real_4 = 4.0
vhdl_sv_wreal.i_sv_sub: sv_real_4 = 4.000000
vhdl_sv_wreal: sv_real_out = 8.000000
vhdl_sv_wreal: vhdl_real_out = 8.000000