Contents

1

Real Number Modeling in Mixed-Signal Designs

Why Real Number Modeling

Introduction to Real Number Modeling

Model Verification

Benefits of Using Real Number Modeling

A RVM-Based Workflow

2

Verilog-AMS Real Number Modeling

Real Net Declarations

Verilog-AMS Wreal Examples

Example 1

Example 2

Example 3

Advanced Wreal Modeling Features

Wreal Arrays

Assigning a Complete Array to Another Array

Connecting Wire Vectors to Wreal Arrays

Wreal X and Z State

Multiple Driven Wreals

Syntax

Example

Wreal Coercion

Wreal Table Models

Wreal Connections to VHDL real and SystemVerilog real

Wreal Connections to the Electrical Domain

Connection to the Digital Domain

Working with Disciplines

Specifying Disciplines to a Design

Defining New Disciplines

Specifying Connect Module and Discipline Definitions

Local Resolution Functions for Disciplines

Real Value Probe Filtering

Enabling Real Value Probe Filtering

3

SystemVerilog Real Number Modeling

SystemVerilog Real Variables

Example

Limitations

SystemVerilog User-Defined Nettype

Built-In Real Nettypes

Built-In Electrical Nettypes

EEnet for Network Evaluation

Declaring Nettypes

Examples of Using Built-In Nettypes

Example: EEnet Driver Module

Example: Single-Value Real without Resolution Function

Example: Scalar Real with Built-In Resolution Function

Example: Typedef Real with Built-In Resolution Function

Example: Built-In Nettypes with X and Z States

Connect Modules for SV-RNM Connections

Connect Modules for SystemVerilog User Defined Nettype (SV-UDN) to Electrical Connections

SV-AMS Connect Modules for UDNUDN, UDN-Logic, and UDN-Real Connections

SystemVerilog Interconnects

Port Connection Rules

4

Modeling with Wreal

Sample Model Library

Analog Functions Translated to Wreal

Wreal Value Sources

Integration and Differentiation

Value Sampling

Slew Limiting

Modeling Examples

Voltage Controlled Oscillator

Low Pass Filter

Event-based and Fixed Sampling Time

ADC/DAC Example

Case Study of Using Wreal Modeling

Appendix A: Advanced Digital Verification Methodology

Verification Plan and Metric-Driven Verification

Metric-Driven Verification and Advanced Testbench

Appendix B: Mixed-Signal Simulation

5

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