The Cadence implementation of the Verilog-AMS language supports more than one driver on a wreal net and the following states for wreal values:
| States | Description |
|---|---|
|
|
High-impedance state equivalent to the hiZ discrete logic state |
`wrealXState |
Unknown state equivalent to the X state in discrete logic. The software sets the value of a |
The concept of an unknown – X and high impedance – Z state used in the 4-state logic is equivalent for the wreal case. `wrealZState and `wrealXState are used to define the related conditions in the wreal context, as shown in the following example.
`include "disciplines.vams"module top(); wreal s; real r; foo f1 (s); initial begin #1 r = 1.234; #1 r = `wrealZState; #1 r = 3.2; #1 r = `wrealXState; #1 r = -4.2; #1 $stop; end assign s = r;endmodule
module foo(a); inout a; wreal a; always @(a) begin if(a === `wrealZState) $display("--> Z"); else if(a === `wrealXState) $display("--> X"); else $display("%f", a); endendmodule
The output result for the above example is shown below:
1.234000--> Z3.200000--> X-4.200000
‘wrealXState and ‘wrealZState are internally defined constants. It is not recommended to overwrite these constants locally; though it is possible.
It is important to use the === operator in these type of comparisons. An a == 1'bx comparison always returns 'x' due to the fact that Verilog does not assume the comparison between two unknown values to be true. Verilog is pessimistic and interprets 'x' as 0 in the conditional statements. The === operator provides the comparison functionality including x and z states.
The output of the above example using the == instead of the === operator would be:
1.234000`wrealZState3.200000`wrealXState-4.200000
In all cases, the simulator would go into the $display("%f", a); condition.
Related Topics
-
"Real Nets with More than One Driver"in the Cadence ®Verilog® -AMS Language Reference Guide.
