Product Documentation

AMS in ADE Explorer FAQ
Product Version IC23.1, June 2023

Contents

AMS Designer in ADE Explorer FAQ

General FAQ on the AMS Designer Interface in ADE Explorer

Which AMS netlisters are available in ADE Explorer to netlist my mixed-signal design?

Which simulation mode is available in ADE Explorer to simulate the netlist created by the AMS UNL netlister flow?

Does AMS Designer support multi-threading capability?

How to compile user defined connect modules?

General FAQ on the AMS UNL Netlister

What is the AMS UNL flow?

What is UNL Verilog-AMS netlister?

How can I set the AMS UNL netlister in ADE Explorer?

What is the name of the netlist file created by the UNL netlister, and where is it located?

Does the UNL netlister also create cellview-level netlists?

Does the UNL netlister also need the implicit/explicit temporary library or writable design library?

Can I save OCEAN scripts for the UNL netlister and run them later?

Is there a command-line executable for the UNL netlister?

What is the advantage of xrun over ncverilog?

What is the advantage of single step simulation (xrun) over 3-step simulation (ncvlog, xmelab, xmsim)?

I want to pass a pre-compiled lib but xrun is not reading from the project directory, what should I do?

FAQ on Migration from SpectreVerilog to AMS Designer

I am using SpectreVerilog and want to migrate to AMS Designer. Which netlister should I use?

I am using SpectreVerilog and want to migrate to AMS Designer. Will my existing design configuration view work with the UNL netlister?

Will the Verilog Library files (-v) and the Verilog Library directories (-y) fields that I use with SpectreVerilog netlister work in the same way with the UNL netlister?

FAQ on the AMS UNL Netlisting Flow

How does the UNL netlister compile Verilog-A files?

Why can't I use SimVision for debugging Verilog-A files when I use the UNL netlister?

UNL Netlister FAQ

How can I use Verilog text files?

How can I use VHDL text files?

Can I use VHDL-AMS text with the UNL netlister?

Can the UNL netlister create a VHDL-AMS netlist?

How does the UNL netlister pass the HDL text files to xrun?

Are the values of -incdir, -v, -y and -f options relative to the current working directory, or relative to netlist directory?

Where are the model files searched?

I chose the Spectre solver, but I see both Spectre control file (amsControlSpectre.scs) and UltraSim control file (amsControlUltraSim.scs) in the netlist directory. Why?

My design has two instances of the same library and cell, one bound to verilog view, and the other to Verilog-A view. Will the UNL netlister netlist and bind the instances correctly?

My design has two instances of the same cell, one bound to verilog view, and the other bound to verilogams view. Will UNL netlister netlist the instances correctly?

My design has two instances of same cell but they are bound to different views (schematic and verilog). Will the UNL netlister netlist the instances correctly?

I see xmelab CUVMUR errors; model name in instance definition is incorrect. What is the solution?

Why do I get SFE-23 errors during UNL Netlisting Step?

What does the Clean snapshot and pak files check box in the Netlist and Run Options form do? When should I use it?

How does the UNL netlister print inherited connections in the netlists?

Where can I find basic information on how to use inherited connections with Cadence tools?

Can the UNL netlister print inherited connections as pseudo ports, like the Spectre and SpectreVerilog netlisters?

Do sideways inhconn netSets work with the UNL netlister?

Miscellaneous FAQ on AMS Designer Interface in ADE and ADE Explorer

How can I get more information on an error from the simulator?

I defined a new value for a variable in the CIW and clicked on the Netlist and Run icon. However, I still see the same incorrect netlist. What is wrong?

I do not have xrun in my older IUS release, but I have the ncverilog executable. Can I use ncverilog with the UNL netlister?

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