You can use the -ahdllint command-line option to turn on the AHDL linter feature that enables you to detect modelling issues in analog/mixed-signal Hardware Description Languages (AHDL). The AHDL linter feature comprises of static and dynamic lint checks. Static lint checks are performed before analysis. Dynamic lint checks are performed during analysis for dynamic modelling issues.
Dynamic lint checks can also be performed on VHDL-AMS modules.
Possible values for the -ahdllint option are:
no - Disables lint checks. There is no change in the existing compilation or simulation warning messages.
warn (default)- Turns on the static lint and dynamic lint checks. Except for the models with attribute ( -ahdllint = no ), the static linter checks all models, continues the simulation, and then performs dynamic lint checks.
error - Turns on the static lint check. Dynamic lint checks are performed only when static lint issues are not detected. Except the models with attribute ( -ahdllint = no ), the static linter checks all models.
The simulator generates an error and exits if there is any static lint warning reported after parsing all the models of the circuit. If there are no static lint warnings, the simulator continues the simulation and performs dynamic lint checks. However, in the case of dynamic lint issues, the simulator does not error out.
force - Similar to warn , but this option overrides the model attribute ahdllint = no , and to check all models, continue the simulation, and perform dynamic lint checks.
You can use the -ahdllint_maxwarn = n command-line option to control the maximum number of static warnings generated per Verilog-A, Verilog-AMS, or VHDL-AMS model. The default value is 5. The -ahdllint_maxwarn option does not limit the warnings generated from the dynamic lint checks.
Use the -ahdllint_log = file_name command-line option to dump all AHDLinter static and dynamic and summary messages to a file.
xmsim stage.Though linter checks are supported for both Verilog-A and VerilogAMS languages, there can be some differences in the behavior. For example, when a declared variable is not used in the model, Verilog-A will generate a lint warning but VerilogAMS will not.
Dynamic lint checks can also be performed on VHDL-AMS modules.
The +cktpreset option, with a possible value of sampled (cktpreset=sampled) enables Spectre or the APS technologies to take fewer time steps during conservative mode simulation while improving simulation resolution at each time step.