xrun Command-Line Options for Mixed-Signal Designs

The xrun command options listed in this topic are the commonly used options for analog and digital mixed-signal design simulations. For the complete set of xrun command options, see Common Options.

To see the set of command-line options (xrunOptions) that relate to AMS simulation, type the following on the command line:

xrun -helpsubject ams

You can use the xrun -helpsubject amsspice to view the xrun options for AMS-SPICE.

xrunOptions	Description
-ams	Force `xrun` to compile all input files as AMS files (Verilog-AMS, VHDL-AMS) regardless of their file extensions. This option indicates that some or all of the HDL design units are written in the Verilog-AMS language. If you do not use this option, `xrun` analyzes for the Verilog language, which is likely to result in many errors when the language is actually Verilog-AMS. For example, to compile the files `ms10.v` and `ms12.v` , which both contain modules written with Verilog-AMS, you can use a command like `xrun -ams ms10.v ms12.v` Be careful to use the `-ams` option only when appropriate. For example, using the option with legacy digital Verilog modules can cause errors if Verilog-AMS keywords are used as identifiers in the Verilog modules.
`-access[+] [-] access_spec`	Sets the visibility access for all objects in the design.
`-ade`	Enable plotting of digital signals in ViVA on digital simulation in ADE flow.
`-afile access_file`	Specifies an access file.
`-amsvivalog`	Generate `runObjFile`. This is useful for several analyses supported by AMS, such as monte carlo analysis that creates multiple log files. In cases where multiple log files are saved in different locations, it is not possible for ViVA to read all the datasets unless there is a `runObjFile` that tells ViVA where to get all the log files from.
`-amsconnrules` `rulesName`	Specify connect rules to use for automatic connect module insertion (for example, between the default `logic` discipline and the `electrical` discipline) You can specify more than one `-amsconnrules` option. The order in which you specify connect rules in their source files determines their precedence. The software must be able to find the named connect rules in one of the source files or precompiled libraries. If you use the Cadence-installed connect rules, you can use an `ie` statement to automate the process of creating a custom discipline and connect rule for connecting the custom discipline to the `electrical` discipline.
`-amsdebug`	Generates readable call stack for the log file.
`-ams_dig_wreal`	Keeps wreal as discrete discipline.
`-ams_dspf_bbox`	Enables the DPSF-in-the-middle flow for AMS simulations in Virtuoso ADE.
`-amsinput spectre_file`	Specifies a Spectre-language file. You can specify more than one Spectre-language file on the `xrun` command line: `xrun -amsi file1.scs -amsi file1.scs`
`-amsoutdir`	Redirect the temporary files and subdirectories created during compilation, elaboration, and simulation to the specified subdirectory . The -amsoutdir option will override the `+amsrawdir`, `-nclibdirpath`, or `-ahdllibdir` settings. It is recommended not to use the `+amsrawdir`, `-nclibdirpath`, or `-ahdllibdir` options when using `--amsoutdir`.
`-amspartinfo` `file`	Specifies a file to hold mixed-signal partition and connect module insertion information. The file also contains information about Real Number Modeling nettype (for example, wrealavg, wrealsum, and so on) in the design. The format of the file might change from release to release.
`-amsdir` `raw_dir`	Specifies the output raw file directory.
`-amselabtrace assert\| digitaloomr\| ssoveride`	Allows to trace nets in a design. You can specify the following values: `assert`: Traces nets that are connected to digital constructs in an assertion statement. `digitaloomr`: Traces OOMR nets that are used in digital context which result in a discrete discipline resolved. `ssoveride`: Generates an error message containing the information about the hierarchical instance port in the digital blocks, if the supplySensitivity attributes are not found in that port when supply-sensitive connect modules are used.
`-amsvhdl_ext` `extension`	Overrides extensions for VHDL-AMS source files.
`-amsvlog_ext` `extension`	Overrides extensions for Verilog-AMS source files. You can also add file extensions to the list of built-in extensions, by specifying a plus sign (+) before the extensions to be added. For example, the following option adds `.va` to the list of built-in file extensions for Verilog-AMS source files: `-amsvlog_ext` `+.va`
`-ams_ucm`	Sets the Universal Connect Module (UCM) to be enabled by default for APS and Spectre X simulation performance mode.
`-ams_weak_setd`	Allows to override the BDR setting on domainless nets to any appropriate discipline.
`-analogcontrol file`	Specifies the analog simulation control file. The analog simulation control file is an ASCII text file written in the Spectre or Spectre control languages. The contents of the file control the behavior of the analog solvers. For example: `xrun top:amsSS -cdslib /SAR_A2D/cds.lib -hdlvar /SAR_A2D/hdl.var -analogcontrol /SAR_A2D/tutorial_run/amsSC.scs`
`-analogsolver`	Lets you specify how to run Spectre. Example: `xrun -analogsolver "spectre"` Runs Spectre on the local host. You can also use a script or a resource scheduler, provided it boots Spectre. `xrun -analogsolver "bsub -R \"OSNAME==Linux &7 OSREL==EE70 && SFIPLATFORM==c0700\" -n 1 -q lnx64 -J spectre"`Runs Spectre on a remote host.
`-anno_simtime`	Enables the use of PLI / VPI routines that modify delays at simulation time.
`-append_log`	Appends log data from multiple runs of `xrun` to one log file.
`-binding[ lib .] cell [: view ]`	Forces an explicit submodule binding.
`-cda_implicit_tmpdir implicitTmpDir`	Writes the compiled design data to `implicitTmpDir`, the implicit TMP directory for all libraries in the design. Establishes a directory to hold any created temporary libraries. This directory is used even when `ASSIGN` statements in the `cds.lib` file specify different directories. For example, your `cds.lib` contains `DEFINE amstestLib ./amstest DEFINE basicLib ./basic ASSIGN basicLib TMP ./basicTMP DEFINE analogLib ./analog ASSIGN AllLibs TmpRootDir ./myTMPs` Without a `-cds_implicit_tmpdir` option in effect, new data is written to `./myTMPs/amstest ./basicTMP/basic ./myTMPs/analog` Using the same `cds.lib` but with the option, `-cds_implicit_tmpdir ./myImplTMPs` in effect, however, writes new data to: `./myImplTMPs/amstest ./myImplTMPs/basic ./myImplTMPs/analog`
`-cds_implicit_tmponly`	When you use this option with the `-update` option, the update operation looks only at design data in the `implicitTmpDir` you specify using the `-CDS_IMPLICIT_TMPDir` option. If you do not use this option, the update operation also considers design data it finds in libraries defined in `cds.lib` files. You can use the `-CDS_IMPLICIT_TMPOnly` option only when you also use the `-CDS_IMPLICIT_TMPDir` option.
`-cdslib cdslib_pathname`	Specifies the cds.lib file to use.
`-chkdigdisp`	Performs discipline compatibility of the digital net.
`-checktasks`	Checks that all $tasks are predefined system tasks.
`-clean`	Deletes the complete set of output files and directories that are created by the tool to perform additional processing of Verilog and SPICE interfaces. These files include the `portbind` files, skeletons, and other AMS Designer-specific processing files.
`-cleanlib`	Deletes all `.pak` files found in the libraries specified in the `cds.lib` file that is located in the current working directory or the `cds.lib` file specified using the `-cdslib` option. It also removes the `./xcelium.d` directory. The `-cleanlib` option searches through the entire `cds.lib` structure and also deletes any additional `cds.lib` files that are included in the original. This option does not remove the `.pak` files that do not have write permissions, or the `.pak` files located in the Cadence Install directory. Use the `-cleanlib` option carefully because it deletes all the writable `.pak` files found in the libraries specified in the cds.lib file even if the libraries are shared with another process.
`-cleanlibverify`	Behaves similarly as the `-cleanlib` option. However, when this option is used, xrun displays the list of files that are being removed and removes the files only after confirmation.
`-cleanlibscript`	This option creates an executable script, which upon executing, produces the same result as the `-cleanlib` option. The script is called `cleanlibscript.sh` and is created in the working directory. After creating the script, xrun exits.
`-coverage`	Enables coverage instrumentation.
`-default_spice_oomr`	Assigns a default value (`1'bx`) when a digital statement contains an out-of-module reference to a SPICE block. See Reusing Mixed-Language Testbenches.
`-define identifier [= value ]`	Defines a macro. See Defining Macros on the Command Line.
`-delay_mode{zero\|unit\|path\|distributed\|none}`	Specifies the delay mode to use for digital Verilog-AMS portions of the hierarchy.
`-desktop`	Specifies that you want to use the desktop simulator after starting the launch program.
`-discipline` `disciplineName`	Specifies the discipline to use for undisciplined digital wires.
`-disres default\|detailed\|none`	Sets discipline resolution.
`-dms_report`	Provides a high-level report of mixed-signal and co-simulation designs. It helps you understand the various design configurations used in a design. See Mixed-Signal Design Debugging Reports.
`-dms_perf`	Enables performance optimizations in some mixed-signal design.
`-epulse_neg`	Filters cancelled events (negative pulses) to the e state.
`-epulse_noneg`	Does not filter cancelled events (negative pulses) to the e state.
`-epulse_ondetect`	Uses On-Detect filtering of error pulses.
`-epulse_onevent`	Uses On-Event filtering of error pulses.
`-errormax integer`	Specifies the maximum number of errors to process.
`-expand`	Expands all vector nets.
`-fast_recompilation`	Enables enhanced recompilation, which improves recompilation and re-elaboration performance when compared to the default flow. When working with a larger design, or a design that requires temporary access to distinct source files, the default recompilation flow can reduce simulator performance or introduce unnecessary recompilation and re-elaboration. Use this option to enable the enhanced recompilation flow, which improves performance and helps to avoid any unnecessary recompilation and re-elaboration introduced by the default flow. You can specify this option on single or multiple xrun command lines. For more information, see the Specifying Enhanced Recompilation section in the Xcelium Xrun User Guide.
`-file arguments_filename`	Specifies a file of command-line arguments to use.
`-gateloopwarn`	Detects zero-delay loop of gate-level Verilog (or VHDL) models and prints the details in the form of proper error messages.
`-genafile access_filename`	Generates an access file with the specified file name.
`-generic generic_name => value`	Specifies a value for a top-level generic.
`-hdlvar hdlvar_pathname`	Specifies the hdl.var file to use.
`-help`	Displays a list of the xrun command-line options.
`+finish_current_analysis`	Specifies `$finish` to finish the current analysis for a multi-analysis simulation.
`-honorvams`	Specifying the `-honorvams` option with the `-sv` option ensures that a VAMS (Verilog-AMS) file extension is considered as a VAMS file and not compiled to a SystemVerilog (SV) file. It overrides all instances of the `-sv` option, which are read in multiple `.f` files, for these VAMS files. For example, in the following scenario, the `-sv` option compiles `foo1`, `foo2`, `foo3` as SystemVerilog files: `> xrun foo1.sv foo2.vams foo3.v -sv` To compile `foo2.vams` as VAMS, add the `-honorvams` option along with the `-sv` option: `> xrun foo1.sv foo2.vams foo3.v -sv -honorvams`
`-ieee1364`	Reports errors according to the IEEE 1364 Verilog standard.
`-iereport/-ieinfo`	The `-iereport`/`-ieinfo` option generates a detailed report containing Interface Element information, Port Discipline, Sensitivity information, Port Drivers information, Conversion Element (CE) name, File, Instance, Generic map, VHDL signal, SPICE node, CE report summary, and so on. See Mixed-Signal Design Debugging Reports. The `-ieinfo` option writes the results in a file `ams_ieinfo.log.` Use the `-ieinfo_log` option to output the results to a different file. The `-iereport` option is aliased to the `-ieinfo` option.
`-ieinfo_driverload`	Generates a Tcl file, `ieinfo_driverload.tcl`, with the drivers and loads information for both CE and IE.
`-ieinfo_driverload_tcl <` `filename` `>`	Generates a user-specified Tcl file that contains drivers and loads information for both CE and IE.
`-ieinfo_log` <`filename`>	Specifies the file to which the results of the `-iereport` are written. If this option is not specified, the results are written to the default `ams_ieinfo.log` file in the current working directory.
`-ieinfo_probe`	Generates a Tcl file `ieinfo_probe.tcl` that contains the probe-related information for both IE and CE.
`-ieinfo_probe_tcl` <`filename`>	Generates a user-specified Tcl file that contains the probe-related information for both IE and CE.
`-ieinfo_summary`	Generates a summarized report containing IE-related information. See Mixed-Signal Design Debugging Reports. The `-ieinfo_summary` option writes the results in a file `ams_ieinfo.log.` Use the `-ieinfo_log` <`filename`> option to output the results to a different file.
`-ignore_analog_tstop`	Ignores the `tstop` setting in the Spectre netlist during an AMS simulation. This ensures that the simulation continues running even after the transient time has exceeded the stop time. When this option is set, the stop time is controlled by the digital simulator. The stop time specified in the Spectre tran statement is still used to initiate the analog solver. For example, the matrix and time step.
`-ignore_missing_spice_port`	Ignores the missing SPICE ports displayed as "not found" in the port bind file.
`-ignore_spice_oomr`	Ignores any digital statements that contain out-of-module references to SPICE blocks See Reusing Mixed-Language Testbenches for more information.
`-ignore_svbind_spice`	Ignores the SV bind statements on SPICE blocks. See SystemVerilog Binding on SPICE for more information.
`-incdir directory`	Specifies an include directory.
`-intermod_path`	Enables multisource and transport delay behavior with pulse control for interconnect delays.
`-lexpragma`	Enables processing of lexical pragmas.
`-libcell`	Marks all cells with `celldefine.
`-libverbose`	Displays messages about module and UDP instantiations.
`-licinfo`	Provides information on the simulation-time licenses required for the specified design. It also provides additional information about the features that are being used for AMSD licensing. The `-licinfo` option generates a report on the licensing requirements using the following parameters: The contents of the design (AMS, SystemC, SystemVerilog, Verilog, VHDL, and so on). Other options specified on the command line. Any arguments specified using the -uselicense option. The `-licinfo` option does not check out any licenses and also does not run the simulation.
`-linedebug`	Enables line debug capabilities.
`-loadpli1 shared_library_name : bootstrap_function_name`	Dynamically loads the specified PLI 1.0 application.
`-loadvpi shared_library_name : bootstrap_function_name`	Dynamically loads the specified VPI application.
`-log_amsspice <log` `file>`	Saves the `amsspice` output file into the specified log file.
`-logfile filename`	Specifies the file to contain log data.
`-maxdelays`	Applies the maximum delay value from a timing triplet in the form min:typ:max in the SDF file while annotating to Verilog or to VITAL.
`-mccodegen`	Enables multi-core code generation for AMS designs and RNM designs. See `-mccodegen`. Analog mixed-signal designs are not supported.
`-messages`	Turns on the printing of informative messages.
`-mixed_bus_opt`	Does not allow mixed buses to be automatically generated for unsupported constructs.
`-mixesc`	Required when elaborating if you instantiate VHDL or VHDL-AMS in a Verilog or Verilog-AMS module and you use escaped entity, port, or generic names within the VHDL or VHDL-AMS descriptions.
`-modelincdir pathname {: pathname}`	Specifies a list of paths to be searched for model files, included files, or files that are passed as instance parameter values.
`-modelpath` `string`	For Verilog-AMS, specify one or more model files, optionally including a model section specifier such as `-modelpath ./models/resistor.scs(res)`
`-neg_tchk`	Allows negative values in `$setuphold` and `$recrem` timing checks in the Verilog description and in `SETUPHOLD` and `RECREM` timing checks in SDF annotation.
`-nettype_port_relax`	Allows for relaxed port compatibility rules for connections of built-in nettypes. See Using Real Number Modeling in SystemVerilog.
`-neverwarn`	Disables printing of all warning messages.
`-no_sdfa_header`	Turns off the printing of elaborator information messages that display information contained in the SDF command file.
`-no_tchk_msg`	Turns off the display of timing check warning messages.
`-no_tchk_xgen`	Turns off X generation in accelerated VITAL timing checks.
`-no_vpd_msg`	Turns off glitch messages from accelerated VITAL pathdelay procedures.
`-no_vpd_xgen`	Turns off X generation in accelerated VITAL pathdelay procedures.
`-noautosdf`	Turns off automatic SDF annotation.
`-nocopyright`	Suppresses printing of the copyright banner.
`-noipd`	Turns off recognition of input path delays in a VITAL level 1 cell and uses the non-delayed input signals directly.
`-noline`	Turns off source line locations for errors.
`-nolog`	Turns off generation of a log file.
`-nonotifier`	Tells the elaborator to ignore notifiers in timing checks.
`-nomempack`	Enables use of the PLI routine `tf_nodeinfo()`, which is used to access memory array values.
`-noparamerr`	Tells the elaborator to allow undeclared parameters to be overridden.
`-noporterr(scope) port_name`	Tells the elaborator to allow the instantiation of design units that do not have all the ports that are specified in the port connection list. For more information, see the `-noporterr` option.
`-nopragmawarn`	Disables pragma-related warning messages.
`-nosource`	Turns off source file timestamp checking when using the -UPdate option.
`-nostdout`	Suppresses the printing of most output to the screen.
`-notimingchecks`	Turns off the execution of timing checks.
`-novitalaccl`	Suppresses the acceleration of VITAL level 1-compliant cells.
`-nowarn warning_code`	Disables printing of the specified warning message.
`-ntc_warn`	Prints convergence warnings for negative timing checks for both Verilog and VITAL if delays cannot be calculated given the current limit values.
`-nowarn <arg>`	Disables printing of the specified warning message.
`-noparamerr`	Disables flag setting undefined parameters as error.
`-no_analog_solver`	Runs the simulation without invoking the Spectre AMS simulator in digital-only logic and RNM simulations. This option is automatically turned on when there is digital-only logic or RNM designs that do not have electrical/SPICE or need ie card (.scs). Also, you can manually specify this option if you do not want to invoke Spectre AMS simulator in a design where ie card (.scs) is available.
`-omicheckinglevel checking_level`	Specifies the OMI checking level to use.
`-pathpulse`	Enables `PATHPULSE$` specparams, which are used to set module path pulse control on a specific module or on specific paths within modules.
`-plinooptwarn`	Prints a warning message only the first time that a PLI read, write, or connectivity access violation is detected.
`-plinowarn`	Disables printing of PLI warning and error messages.
`-pragma`	Enables pragma processing.
`-preserve`	Preserves resolution functions on signals with only one driver.
`-propspath path`	Specifies the path to the `prop.cfg` file. However, `prop.cfg` is no longer supported; therefore, you must convert to amsd Block. See Appendix E: Migration of prop.cfg file to an amsd Block. Alternatively, you can instruct the internal translator to convert your `prop.cfg` file to an amsd block file, `prop.cfg.scs`, by setting the AMSCB environment variable.
`-ppe`	Invokes the post-processing environment (PPE) See Running the SimVision Analysis Environment for more information.
`-propspath` `path`	Specifies analog occurrence property database file
`-pulse_e error_percent`	Sets the percentage of delay for the pulse error limit for both module paths and interconnect.
`-pulse_int_e error_percent`	Sets the percentage of delay for the pulse error limit for interconnect only.
`-pulse_int_r reject_percent`	Sets the percentage of delay for the pulse reject limit for interconnect only.
`-pulse_r reject_percent`	Sets the percentage of delay for the pulse reject limit for both module paths and interconnect.
`-q`	Suppresses all informational messages (quiet mode).
`-relax`	Enables relaxed VHDL interpretation.
`-rnm_coerce default\| none\|` `detailed\| on\|off scopeType-scope-`	Enables or disables wreal coercion globally and/or on certain design scopes. You can turn off wreal coercion: On a specific instance and instances under it. For instances whose master is specific module and instances under the module. On specific nets. You can turn on wreal coercion: On a specific instance and instances under it. For instances whose master is specific module and instances under the module. It is not supported on scopetypes: `lib`, `cellterm`, `instterm`, `net`, and `cellupport`. Possible values are: `none`: Disables wreal coercion globally. `detailed`: Enables wreal coercion with detailed resolution. This is the default. `default`: Enables global coercion with default resolution. `on/off scopeType -scope-`: Enables wreal coercion on specific scope. You can use `on scopeType -scope` to enable wreal coercion on the specified scope, when coercion is disabled on other scopes. Likewise, you can use `off scopeType -scope` to disable wreal coercion on a specified scope, when coercion is enabled on other scopes. RNM (wreal) coercion on specific scope is not supported in incremental elaboration single xrun flow. When specifying the `scopeType -scope` value as `off`, you can specify the `-dms_perf` command-line option for performance optimization. Programmable coercion off is supported on scopeTypes: `net inst`, `insterm`, `cell`, `cellterm`, or `lib`. For example: `"NET- hierarchical_net_name -"` `"INSTTERM- hierarchical_port_name -"` `"INST- hierarchical_instance_name -"` `"CELLTERM-l ib_name.cell_name.port_name -"` `"CELLTERM- cell_name.port_name -"` `"CELL- lib_name.cell_name:view_name -"` `"CELL- lib_name.cell_name -"` `"CELL- cell_name -"` `"LIB- lib_name -"` Example: `rnm_coerce "off inst-top.dcinst-"` All the net of instance `top.dcinst` and its children will not be coerced to wreal; top level and other instances will be coerced as normal. The functionality of `insterm` assignment has been merged into net, for the same scope. Therefore, if you specify both the assignments, the `net` assignment takes higher precedence. However, if the `net` assignment is not specified, the `insterm` assignment is considered. If `scopeType` is not specified, the behavior would be similar to the `none` option, and wreal coercion is disabled. Coercion of a wire is performed for the entire wire (bus). Coercion is not supported at bit-level for a bus. If multiple `-rnm_coerce` options are specified for the same design scope, the one specified with the immediate design scope takes precedence. If you are a digital-centric user running an AMS simulation that requires only the digital solver, it is recommended to specify `-rnm_coerce none.`
`-rnm_tech`	Enables Real Number Modeling (RNM) in Elaboration Mode. The option enables you to compile and elaborate structural netlists/file in SystemVerilog (`.sv` file) while applying the concepts of 'implicit' interconnects and RNM coercion; thereby, providing a behavior that is equivalent to structural netlists in Verilog-AMS (`.vams` files).
`-rnm_type_priority <type_list>`	Allows you to specify the precedence order for choosing the type of coercion for an interconnect net when it connects to different nettypes of ports. You can specify the multiple types, without space, separated with the greater than symbol (`>`), comma (`,`) or hyphen (`-`). For example: `-rnm_type_priority wrealsum>wrealmax>wrealavg` or `-rnm_type_priority wrealsum,wrealmax,wrealavg` or `-rnm_type_priority wrealsum-wrealmax-wrealavg` In this example, if a nettype of wrealsum is present in the connection, it gets priority and the wire is coerced as wrealsum. You must specify the `-rnm_tech` option along with the `-rnm_type_priority` option to enable coercion. See `-rnm_tech`.
`-scope_discipline` `disc_scope`	Specifies one scope-based discipline.
`-sdf_cmd_file sdf_command_file`	Specifies an SDF command file to control SDF annotation.
`-sdf_no_errors`	Suppresses error messages from the SDF annotator.
`-sdf_no_warnings`	Suppresses warning messages from the SDF annotator.
`-sdf_nocheck_celltype`	Disables celltype validation between the SDF annotator and the Verilog description.
`-sdf_precision argument`	Modifies SDF data to this precision.
`-sdf_verbose`	Includes detailed information in the SDF log file.
`-sdf_worstcase_rounding`	Truncates the min value, rounds the typ value, and rounds up the max value for the timing values in the SDF file.
`-setdiscipline[no_dr] disc_scope disc_name`	Specifies a discipline for the elaborator to use for domainless nets in the specified scope. Using `no_dr` turns off discipline resolution in the specified scope and for the entire block. And, the `no_dr` option cannot be used in a block that has nets with explicit discipline.
`-shm_filter_group <precision>`	Enables real value filtering for all real value probes. You can specify a precision (delta value) for real number probes to remove recorded values whose delta is less that the precision specified. For more information, see Enabling Real Value Probe Filtering.
`-simcompatible_ams compat_val`	Specifies whether to set simulation values for compatibility with the Spectre language or with the HSPICE language. The default is `hspice.` Specifies the compatibility setting for simulation values. Valid settings are as follows: `spectre`: Spectre-compatible simulation values `hspice`: HSPICE-compatible simulation values The default is `hspice`. The simulation values are as follows: `-simcompatible_ams hspice` `tnom` and `temp` are set to 25C Parameter inheritance is set to global, so that global parameter definitions override local ones. Forces IC statements and initial conditions on elements for DC and OP analyses. `-simcompatible_ams spectre` `tnom` and `temp` are set to 27C Parameter inheritance is set to local only Forces initial conditions only when you set the DC analysis `force` option In addition, for `-simcompatible_ams hspice`, flags on all device models are set to be SPICE compatible. For example: `xrun -simcompatible_ams hspice top:amsSS` The simulator uses these values regardless of which language you use. The `-simcompatible_ams` option does not affect parsing. If you want to add SPICE commands in model files or in the analog simulation control file, you must use the statement, `simulator lang=spice` to specify the language for the statements that follow.
`-snapshot snapshot_name`	Specifies a name for the simulation snapshot. If you do not use this option, `xrun` places the snapshot in the view directory of the first design unit specified on the command line, even when the first design unit is a configuration.
`-solver spectre \| aps`	Specifies whether the Spectre solver, or the APS solver is to be used with the AMS Designer simulator. If this parameter is not specified with the `xrun` command, the Spectre solver is used by default.
`-specificunit[ lib .] cell [: view] filename]`	Compiles the specified unit from the source file.
`-spectre_args`	Specifies one or more Spectre command-line arguments. You can also include multiple entries of the `-spectre_args` parameter on the command line, which are concatenated during command processing. Note: `-spectre_args` is ignored if APS solver is selected.
`-spectre_argfile_spp filename`	Specifies the path to a file containing space-separated command arguments for `spp.` You do not need this option if you are using the simulation front end (SFE) parser.
`-spectre_e`	Runs Spectre parser with the `-E` option
`-spectre_path`	This option is used in the AMSD flex mode to specify the directory where `spectre` and `spectre_root` are located. These can be original binaries from an installation directory or wrapper scripts provided by the user. `xrun` runs the `spectre_root` executable from the specified path to locate the Spectre installation and this location is used to run the simulations. Syntax: `xrun -64... -spectre_path <path_to_spectre> ...` Here, <`path_to_spectre>` can be the path to Spectre installation or path to a Spectre wrapper script. If `-spectre_path` points to a Spectre wrapper script, the following requirements must be met: The Spectre wrapper should be an executable. Wrapper for `spectre_root` should be provided at the same location as the Spectre wrapper. The `spectre_root` wrapper should also be an executable and it should only echo the output of the installed `spectre_root`. Example of Wrapper Script Usage: The following examples illustrate how `spectre and` `spectre_root` should be wrapped in a scenario where a specific user group is to be assigned to use Spectre 18.1 and all the other users are to use Spectre 19.1. spectre wrapper `#!/bin/sh` `if [ "$USER" == "<username>" ]` `then` `spectreInstallDir=/<spectre_installation_dir>/18.1_ISR13` `else` `spectreInstallDir=/<spectre_installation_dir>/19.1_ISR4` `fi` `$spectreInstallDir/bin/spectre “$@”` spectre_root wrapper `#!/bin/sh` `if [ "$USER" == "<username>" ]` `then` `spectreInstallDir=/<spectre_installation_dir>/18.1_ISR13` `else` `spectreInstallDir=/<spectre_installation_dir>/19.1_ISR4` `fi` `$spectreInstallDir/bin/spectre_root “$@”`
`-spectre_spp`	Runs the Spectre parser with `spp` on when parsing files specified by the `-MODELPath` option. You do not need this option if you are using the simulation front end (SFE) parser.
`-spectre_validated`	Lists the Spectre versions compatible with the current Xcelium release. Example: `xrun –spectre_validated` => `Spectre 19.1.0.123.isr18` To view the Xcelium versions validated with the current Spectre release, use the spectre option `–xcelium_validated_version`. Example: `spectre -xcelium_validated_version` `=> Xcelium 20.09-s016`
`-spice_ext` `extension`	Overrides extensions for Spectre and SPICE source files. See Using xrun with Spectre and SPICE Input Files.
`-status`	Prints statistics on memory and CPU usage.
`-sysv_ext extension`	Compiles custom file extension as SystemVerilog file. For example, the following option compiles with a `.dvams` file extension as an SV file: `-sysv_ext .dvams`
`-top` `top_unit`	Specifies `top_unit` as the top-level design unit. You must use `-top` if the top level of your design is VHDL. Note: `xrun` automatically determines the top-level design unit from Verilog or SystemVerilog source files. See -top. For more information about using `-top` to specify connect modules and `cds_globals`, see "Compatibility with Existing Use Models".
-timescale`time_unit / time_precision'	Sets the default timescale for Verilog (digital) modules that do not have a timescale set.
`-typdelays`	Applies the typical delay value from a timing triplet in the form min:typ:max in the SDF file while annotating to Verilog or to VITAL.
`-unit[ lib .] cell [: view ]`	Specifies the unit to be compiled.
`-upcase`	Changes all identifiers (including keywords) to upper case (case-insensitive). Using this option can cause conflicts. For example, if you use this option, you must create and use a case-insensitive version of the disciplines.vams file that distinguishes `Voltage` nature from `voltage` discipline and `Current` nature from `current` discipline. In addition, using this option causes a clash between the `Force` nature and the `force` keyword.
`-update`	Recompiles out-of-date design units. The `-CDS_IMPLICIT_TMPOnly` option affects the behavior of the `-update` option.
`-uselicense mnemonic_list`	Specifies a custom prioritized license checkout order for simulation. For example: `-uselicense mnemonicList [:DEFAULT]` where `mnemonicList` is a colon-separated list of one or more valid mnemonic keywords. The optional DEFAULT mnemonic indicates the default license selection, which includes digital-specific license mnemonics. For more information about these and other digital-specific mnemonics, see Product and Licensing Information for Mixed-Signal Designs. The -`uselicense` option has been deprecated in the XCELIUM 16.11 release.
`-v93`	Enables VHDL-93 features.
`-version`	Prints the compiler version number.
`-view view_name`	Specifies a view association.
`-vipdmax`	Selects the Max. delay value for VitalInterconnectDelays.
`-vipdmin`	Selects the Min. delay value for VitalInterconnectDelays.
`+wf_alias`	Using this option enables the waveform aliasing feature, which improves the waveform database size by leveraging the alias semantics for waveform storage. The `+wf_alia`s option would be removed in a future release.
`-work library`	Specifies the library to be used as the work library.
`-wreal_resolutionresolutionFunction`	Specifies the `wreal` resolution function you want the elaborator to use; valid values for `resolutionFunction` are: `default` - Default setting `fourstate` - Verilog 4-state logic resolution algorithm `sum` - Summation of all drivers `avg` - Average of all drivers `min` - Minimum value of all drivers `max` - Maximum value of all drivers
`-wreal2vhdlmap` `file`	Maps VHDL analog X/Z states with the Verilog wrealZ/X states. You can specify the VHDL/wreal X and Z state mappings in a `file.` The template format is in the form of wreal2vhdlmap card which defines the mapping for the specified VHDL data type. Multiple wreal2vhdlmap cards can be specified in the file. See Mapping Analog X/Z States with Verilog wrealZ/X States..
`-wreal2vhd_probe`	Generates a TCL probe file named, `wreal2vhd_probe.tcl` file. It probes the Wreal and VHDL ports where `xrun` code implements the wreal2vhdl mapping.
`-zparse SKILL_file`	Enables zparsing. The `SKILL_file` argument specifies the name of the SKILL file this option creates for importing Verilog-AMS text modules into the Virtuoso^®design environment.

xrun Command-Line Options for Mixed-Signal Designs

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