By default, the elaborator enables full access to digital simulation objects in the VHDL portion of a design. In addition, you always have full access to analog objects.
However, the elaborator marks all digital objects in a Verilog-AMS design as having no read or write access and disables access to connectivity (load and driver) information. Turning off these three forms of access allows the elaborator to perform a set of optimizations that can dramatically improve the performance of the digital solver.
The only exceptions to this default mode are digital objects that are used as arguments to user-defined system tasks or functions. These objects are automatically given read, write, and connectivity access. By default, no access is given to objects that are used as arguments to built-in system tasks or functions. Using a construct that does not have a value (a module instance, for example) as an argument has no effect on access capabilities.
Generating a snapshot with limited visibility into simulation constructs and running the simulation in regression mode has significant performance advantages. However, turning off access to the HDL data structures imposes the following limitation: You cannot access simulation objects from a point outside the HDL code, through Tcl commands or through PLI.
You can turn on read, write, and connectivity access by using the following elaborator xrun command-line options:
-ACCEss: Use this option to specify the access capability for all objects in the design.-AFile: Use this option to include an access file in which you specify the access capability for particular instances and portions of the design.