Binding During Mixed-Signal Design Elaboration

Binding is the process of selecting which design units are instantiated at each location in the design hierarchy. For mixed-signal designs, a design unit might be a module, UDP, or analog (SPICE or Spectre) block. The elaborator binds each design unit that you instantiate in another, higher-level design block (such as a module) to a particular Library.Cell:View.

• The default binding mechanism
• The xmelab -binding option, which you can use to force the binding of a cell to a particular library and view
• The `uselib compiler directive, which lets you override the default binding mechanism and all command-line options

• The xmelab -modelpath option, which lets you specify SPICE or Spectre source files for the models to be used in a specified scope and in scopes below the specified scope

These binding mechanisms do not apply to the top-level modules that you specify on the command line.

For the AMS Designer simulator, the binding priorities are as follows (from highest to lowest):

1. The following subset of analog primitives from the Verilog-AMS LRM or any analog block (defined as a SPICE netlist or Verilog-A module) you specify using the sourcefileproperty in amsd.scs:
   resistor
capacitor
inductor
tline
vcvs
vccs
2. 5x config rules
3. -modelpath setting

Related Topics

• Elaboration Command-Line Options
• -modelpath