Connecting SystemVerilog Hierarchical UDT to Electrical

In addition to connecting SystemVerilog wreals to electrical nets, you can connect hierarchical user-defined types (UDTs) to Electrical nets. To connect hierarchical UDTs to electrical nets, use the -sv_ms option on the xrun command-line option. Hierarchical UDT including arrays of packed structure nettype, logic bit types (logic single type and bit select of logic bus), and L2E/E2L connect modules are supported. The following are the integer datatypes that are supported:

L2E and E2L connect modules are used to setup hierarchical UDTs to Electrical port connections. However, LE_Bdir connect module is not supported because logic and reg types cannot connect to inout electrical/spice port.

Also, note that the following types of port connections are not supported:

• Connections containing multi-dimensional array
• Concatenation and replicate concat connections
• L/R related IE, or R/E related IE
• Connections to wreal/real ports, which lead to L/R interface elements

Consider the following example of a Verilog testbench where a hierarchical structure is defined. It also illustrates a UDT, new_s of the hierarchical structure connecting to two instances of electrical port, inv.

//top.sv

module top();
typedef struct packed {
   logic [1:0] a;
   logic [2:0] b;
} new_s;

new_s ns1;
typedef struct  packed {
logic aa;
   new_s new_s_var;
} new_s_level2;

new_s_level2 nsl2;
logic [0:1] as1;
logic w_in;
logic w_in_2;
inv   D_not2b (w_out, nsl2.new_s_var.b[0]); // instance with 
inv   D_not2b_2 (w_out_2, nsl2.new_s_var.a[1]);
…

endmodule

And, the following is an example of the AMSD control file containing SPICE information:

amsd {
    // IE DEFINITIONS DEFAULT
    ie vsup=1.6
    // PARTITIOINING
    config cell=inv use=spice
}

Related Topic

• Features Enabled Using the -sv_ms Option