You can now enable the following SystemVerilog mixed-signal verification functionalities using a single xrun command-line option, -sv_ms:
- Connecting SystemVerilog Hierarchical UDT to Electrical
- Coercion for SystemVerilog Interfaces, Program, or Checker Blocks
- Using Wildcard‐Named Port Connections in SV Bind Statements
- Connecting SystemVerilog Interface to DMS/Verilog-AMS (Electrical) Signals
- Connecting SystemVerilog Multi-Dimensional Array to SPICE/Electrical Ports
The -sv_ms option is a super-set of the -adv_ms option; all features documented in the Features Enabled Using the -adv_ms Option topic can be enabled using the -sv_ms option also.