Connecting SystemVerilog Variable Logic Vector to SPICE Bus

In mixed-signal designs, to connect a SystemVerilog logic vector to a SPICE electrical bus, use the -adv_ms option. The tool then generates a wire bus port as a wrapper and maps the wire bus to the electrical nodes.

The following is an example of an SV logic vector connecting to a SPICE electrical bus:

-------------top.sv-----------

`timescale 1ns/1ps

module top;
   real i[3:0];
   real o[3:0];
    spice_middle x0 ( i,o);
   //initial #3 $display("==== ", i,,o);

Endmodule

------ spice.scs-----------

subckt spice_middle ( i_3 i_2 i_1 i_0 out\<3\> out\<2\> out\<1\> out\<0\>)
v7 ( i_3 0) vsource dc=5
v6 ( i_2 0) vsource dc=5
v5 ( i_1 0) vsource dc=5
v4 ( i_0 0) vsource dc=5
v3 (out\<3\> 0) vsource dc=5
v2 (out\<2\> 0) vsource dc=5
v1 (out\<1\> 0) vsource dc=5
v0 (out\<0\> 0) vsource dc=5
ends

Connecting SystemVerilog Variable Logic Vector to SPICE Bus

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