In a SPICE port to bus element connection, when you use the cellport scopetype for cell port definitions, to apply an interface element parameter specification to specific connect modules, specify the -adv_ms option. This ensures that the parameter specification is applied only to the targeted connect module and not to every connect module on the bus.
The following example illustrates that discipline 1.8 is set to top.in[0]. And, the default discipline (vsup=5) is applied to the other ports top.in[1] and top.in[2].
//top.svmodule top;reg clk = 0;wire ain;wire [0:2] in;always #5 clk=~clk;assign in[0] = clk;assign in[1] = clk;assign in[2] = clk;assign ain = clk;spice_dut I0(in,ain); //SPICE Instanceendmodule
//ana_gate.sp.subckt spice_dut in_0 in_1 in_2 ainxinv0 in_0 out_0 inv_1p8xinv1 in_1 out_1 inv_5xinv2 in_2 out_2 inv_5xinv3 ain aout inv_5.ends
//amscf.scsamsd {portmap subckt=spice_dut autobus=yes file="./spice_dut.pb"config cell=spice_dut use=spice// IE Cards}
amsd {ie vsup=5.0ie vsup=1.8 cellupport=spice_dut.in_0;}
In the first case, discipline, 1.8 is set for top.in along with top.in[0]. In the second instance also, for top.in, top.in[0], and top.in[1] the discipline set is 1.8.The following ie card specification illustrates that when there is no default discipline set and only one bit is set, or multiple bits are set the same discipline, then the bus discipline is merged into one.
amsd { ie vsup=1.8 cellupport=spice_dut.in_0;}
or
amsd { ie vsup=1.8 cellupport=spice_dut.in_0; ie vsup=1.8 cellupport=spice_dut.in_1;}
The following ie card specification illustrates that when there is no default discipline and multiple bits are set to the different discipline, then no discipline is set to the unset bits. In this case, discipline 1.8 is set for top.in[0] and 2.8 is set for top.in[1].
amsd {ievsup=1.8 cellupport=spice_dut.in_0;ievsup=2.8 cellupport=spice_dut.in_1;}