Depositing Values to Signals

You can ask "what if" questions about your model as you debug by interactively depositing a value to a specified object.

When you deposit a value to an object, behaviors that are sensitive to value changes on the object run when the simulation resumes, just as if the value change was caused by the Verilog-AMS or VHDL code.

You can deposit a value to an object immediately, at a specified time in the future, or after a specified delay. You can also specify that you want to deposit the value after an inertial delay or after a transport delay. A deposit without a delay is similar to a force in that the specified value takes effect and propagates immediately. However, it differs from a force in that future transactions on the signal are not blocked.

For VHDL, you can deposit to ports, signals, and variables if no delay is specified. If a delay is specified, you cannot deposit to variables or to signals with multiple sources.

For Verilog-AMS, you can deposit to ports, signals (wires and registers), and variables.

For Verilog-AMS, the object that you want to deposit a value to must have write access. An error is printed if it does not. To specify write access, use the -access or -afile option when you elaborate the design with xmelab. 

To deposit a value to an object,

• If you are using the Tcl command-line interface, type deposit.

• If you are using SimVision, choose Simulation - Deposit Value.