Breakpoints

You can interrupt the simulation by setting breakpoints. The type of breakpoints you can set depend on the language you are using as follows:

Breakpoint Type	Verilog-AMS	VHDL
Condition breakpoints	Yes	Yes
Line breakpoints	Yes	Yes
Signal breakpoints	Yes	Yes
Time breakpoints	Yes	Yes
Subprogram breakpoints	Yes	Yes
Process breakpoints	No	Yes

Setting a Condition Breakpoint

A condition breakpoint stops the simulation when a specified condition is true. This type of breakpoint is particularly useful when you want to stop the simulation at the instant a signal has an incorrect value.

A condition breakpoint triggers when any digital object referenced in the conditional expression changes value (wires, signals, registers, and variables) or is written to (memories) and the expression evaluates to true (nonzero). Condition breakpoints are not triggered by changes in analog objects, but you can include analog objects in the conditional expression and their values are used when the condition is evaluated (due to a digital object changing value).

To set a condition breakpoint,

If you are using the Tcl command-line interface, type stop -condition.

If you are using SimVision, choose Simulation - Set Breakpoint - Condition.

A condition breakpoint takes a Tcl expression as an argument.

The simulator does not support breakpoints on individual bits of registers. If a bit-select of a register appears in the expression, the simulator stops and evaluates the expression when any bit of that register changes value. The same holds true for compressed wires.

For Verilog-AMS, objects included in a conditional expression must have read access. An error is printed if the object does not have read access.

Setting a Line Breakpoint

A line breakpoint stops the simulation at a specified line in the source code. You set this type of breakpoint when you want to simulate to a certain point and then single-step through lines of code.

You cannot set a line breakpoint unless you have compiled with the -linedebug option.

You can set a line breakpoint only in pure digital code when you are using AMS Designer simulator with the Spectre solver and the simulation front end (SFE) parser.

To set a line breakpoint,

If you are using the Tcl command-line interface, type stop -line option.
If you are using SimVision, choose Simulation - Set Breakpoint - Line.

Setting a Signal Breakpoint

A signal breakpoint stops the simulation when a specified wire or signal changes value or when the simulation writes a value to a register, memory, or variable. Use a signal breakpoint when you want the simulation to stop every time a signal changes value or when you want to see the value of signals when some condition is true (for example, on every positive edge of the clock).

To set a signal breakpoint,

If you are using the Tcl command-line interface, type stop -object.

If you are using SimVision, choose Simulation - Set Breakpoint - Signal.

For Verilog-AMS, the object specified as the argument must have read access for the breakpoint to be created.

The simulator does not support breakpoints on analog objects (nets, branches, or variables). Nor does the simulator support breakpoints on individual bits of registers or variables. For example, the following command generates an error message:

xcelium> stop -create -object data[1]

Setting a Time Breakpoint

A time breakpoint stops the simulation at a specified time. The time can be absolute or relative (the default). Absolute time breakpoints are automatically deleted after they trigger. Relative time breakpoints are periodic, stopping, for example, every 10 ns.

This type of breakpoint is usually set when you want to advance the simulation to a certain time point before beginning to debug or when you want to stop the simulation at regular intervals to examine signal values.

To set a time breakpoint,

If you are using the Tcl command-line interface, type stop -time.
If you are using SimVision, choose Simulation - Set Breakpoint - Time.

Setting a Process Breakpoint

For VHDL, a process breakpoint stops the simulation when a named process starts executing or resumes executing after a wait statement.

You must compile with the -linedebug option to enable the setting of source line and process breakpoints.

To set a process breakpoint,

If you are using the Tcl command-line interface, type stop -process.
If you are using SimVision, choose Simulation - Set Breakpoint - Process.

Setting a Subprogram Breakpoint

For VHDL or Verilog, a subprogram breakpoint stops the simulation when the simulation reaches a VHDL or Verilog function or procedure. You can then use the step command to step into the function or procedure to view values of objects.

To set a subprogram breakpoint,

If you are using the Tcl command-line interface, type stop command with the -delta option.

If you are using SimVision, choose Simulation - Set Breakpoint - Subprogram.