Enabling SystemVerilog Interface in LP-MS Designs

To enable SystemVerilog (SV) interface in low-power mixed-signal designs, use the -lps_sv_interface_port option. This ensures that the mixed-signal processing complies with the LP SV interface infrastructure:

• AMS discipline resolution processing
• DMS coercion processing
• Connect module net/port database

Related Topics

• Using the IEEE 1801 Standard in Mixed-Signal Designs
• Power Smart Connect Modules for IEEE 1801