SystemC® is the industry standard for system-level design modeling; it supports the description of the architecture of complex systems consisting of both software and hardware components. The SystemC library provides the constructs necessary to model system architecture, including hardware timing, concurrency, and reactive behavior.
You can simulate and debug a design mixed with SystemC and Verilog or VHDL. Xcelium simulator with mixed-signal option provides support for instantiating Verilog (digital), Verilog-AMS, VHDL (digital), and VHDL-AMS modules inside SystemC models.