Incremental Elaboration at SV-RNM Partition Boundary

Incremental elaboration is enabled for designs containing SystemVerilog User Defined Nettype (SV-UDN) ports at the partition boundaries. You can specify UDN ports at the primary partition boundary of a design; then, the UDN ports from the different secondary partitions are connected and merged into one simulation net.

Verilog-AMS and Spice instantiations can be instantiated within partitions; however, these ports are not allowed across partition boundaries.

The following example enables IE for the SV-UDN port type and xrun compiles the top.sv file. Module, top is the incremental partition and driver1 is the primary partition:

xrun -clean top.sv -primtop driver
//top.sv
//incremental
module top;
WUDNTYPE w;
assign w = 1.1;
driver1 d1(w);
endmodule

//primary
module driver1 (dr_1);
input dr_1;
WUDNTYPE dr_1;
Endmodule

The following are the port types that are supported for incremental elaboration at SV-RNM partition boundary:

sv wreal. For example:

import cds_rnm_pkg::*;
wrealsum w;
or
wrealavg w;

nettype real with UDR. For example:

function automatic real FUNC(input real drivers[]);
begin
FUNC = 1.0;
foreach (drivers[j])
begin
$display("\nFUNC : drivers[%d] = {%f} ", j, drivers[j]);
FUNC += drivers[j];
end
end
endfunction

// A nettype declaration with datatype
nettype real WUDNTYPE with FUNC;

net type struct with one real filed, with UDR. For example:

typedef struct {
real V;
} Rstruct;

function automatic Rstruct FUNC(input Rstruct drivers[]);
begin
FUNC = '{1.0};
foreach (drivers[j])
begin
$display("\nFUNC : drivers[%d] = {%f} ", j, drivers[j].V);
FUNC.V += drivers[j].V;
end
end
endfunction

// A nettype declaration with datatype
nettype Rstruct WUNDTYPE with FUNC;

nettype struct with multiple fields. For example:

typedef struct {
real field1;
real field2;
}T;

// user-defined resolution function Tsum
function automatic T Tsum (input T driver[]);
begin
Tsum.field1 = 0.0;
Tsum.field2 = 0.0;
foreach (driver[i])
begin
$display("driver[%d]{%f}{%f}", i, driver[i].field1, driver[i].field2);
Tsum.field1 += driver[i].field1 ;
Tsum.field2 += driver[i].field2 ;
end
$display("Tsum{%f}{%f}", Tsum.field1, Tsum.field2);
end
endfunction

// A nettype declaration with datatype and resolution function
nettype T WUDNTYPE with Tsum;
OR:
import EE_pkg::*;
EEnet w;

nettype without UDR. For example:

nettype real WUDNTYPE;

The following are the restrictions of using SV-UDN ports at the partition boundaries:

If one side of the connect is UDN and the other side cannot be UDT (struct variable).
Wreal type in .vams connection is not supported. In such cases, you must transfer .vams to .sv; and, use SV Wreal.
Datatype connections such as real connect to non-real, UDN connect to non-UDN are not supported at partition boundaries.
Interconnect coercion to nettype that is already elaborated in a primary partition is not supported.
Discipline resolution of electrical nets at partition boundary.

Incremental Elaboration at SV-RNM Partition Boundary

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