Mixed-Signal Design Debugging Reports
The following table lists the xrun command-line options and the various reports that you can generate for debugging purposes.
-dms_report |
Provides a high-level report of mixed-signal and co-simulation designs. It helps you understand the various design configurations used in a design such as AXUM SPICE, electrical, Verilog-AMS, VHDL-AMS, SV-AMS, SV interconnect, SV-UDN, $cged module, Inherited connections, IE card, coercion, autospiceoomr, $real_net_alias, RNM Randomization, RNM Coverage, mixed-signal array of instances (AOI), VHDL + SPICE flow, SV Interface Interact, SV Bind Interact, SV Logic variable/Real variable to Electrical, Electrical IE, Built-in IE, SV UDN IE, Testbench Reuse (Virtuoso IP or SV) using DMS binding, and AMS UNL using DMS binding.
The following is an example of a report generated using -dms_report:
TOOL: xmelab 22.08-a071-20220815
DMS Design Report generated for 'worklib.top:vams':
The following mixed signal related content was processed (high level report):
Mixed Signal AOI: YES
SPICE files: YES
Verilog-AMS files (with electrical): YES
Verilog-AMS files (with wreal generic): YES
RNM randomization: YES
RNM coverage: YES
Coercion counts:3
Autospiceoomrs counts:1
If the elaboration terminates unexpectedly, the report generated may be incomplete and a note would be included in the report indicating this.
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-iereport/-ieinfo |
The -iereport/-ieinfo option generates a detailed report containing Interface Element information, Port Discipline, Sensitivity information, Port Drivers information, Conversion Element (CE) name, File, Instance, Generic map, VHDL signal, SPICE node, CE report summary, and so on. For example:
Interface Elements at the block <instance> testbench.msbuf.I2 of <master> ana_nand (file : /home/bcui/BDR_multpwr/source/analog/ana_nand.vams)
Automatically inserted : testbench.msbuf.I2.Y1__E2L__logic18V
Connect Module : E2L
Mode : Merged
Net : testbench.msbuf.I2.Y1 (discipline: discrete_amslps, nettype: wrealsum)
Port : testbench.msbuf@ms_buf<module>.I2@ana_nand<module>.I1@my_inv<module>.in (logic18V input)
Parameters:
vsup : 1.8
List of Ports connected to net testbench.msbuf.I2.Y1 : (Total: 1)
testbench.msbuf.I2.I1.in (logic18V input)
Discipline of Port (Din): discrete_amslps, Wreal Port
Drivers of Port Din: tb.dut.PMUInst) assign wvdd1= vsup1
IEEE1801 Power Supply net
CE #1: Name: MY_AD_LIB.E2ILOG:behavior
File: E2ILOG.vhms
Instance: :vh_top:test1:e2ilog_a
Generic Map: ()
VHDL Signal: output ':vh_top:A' with type 'ilog'
Spice Node name: dummy_spice.A
---- CE Report Summary:
E2ILOG ( ELECTRICAL inout; ILOG out; ) total: 1
ILOG2E ( ILOG in; ELECTRICAL inout; ) total: 1
The -ieinfo option writes the results in a file ams_ieinfo.log. Use the -ieinfo_log option to output the results to a different file.
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-ieinfo_summary |
Generates a summarized report containing IE-related information. For example:
1. Interface Elements at the block <instance> top of <master> top (file : ./top.sv)
Automatically inserted : top.\b_zero_pad_bit0__R2E_2__electrical
Connect Module : R2E_2
Mode : Merged
Net : pad connection (discipline: logic, nettype: variable)
Port : top.ana_gate@analog_top<module>.\itune[1] (discipline: electrical, direction: input, nettype: electrical)
Parameters :
vsup :5
vd elta :0.078125
vlo :0
vx :0
tr :5e-11
tf :5e-11
ttol_t :5.000000000000001e-12
tdelay :0
rout :200
rx :200
rz :10000000
Discipline of Port (Din): logic, Wreal Port
Discipline of Port (Aout): electrical, Analog Port
Sensitivity information:
No Sensitivity info
IE Report Summary (with disciplines and directions):
R2E_2 ( logic input; electrical output;) total: 3
--------------------------------------------------------------------
Effective Number of IE Instances:
Total Number of Connect Modules : 3
The -ieinfo_summary option writes the results in a file ams_ieinfo.log. Use the -ieinfo_log <filename> option to output the results to a different file.
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