Verilog ® -AMS modules can contain unnamed branches. For example, you might have:
electrical a, b; V(a,b) <+ 7 * I(a,b) ; // Uses an unnamed branch across a and b
To refer to the unnamed branch when you use a Tcl command, you use an underscore between the two nets. So you might have a Tcl command and response like the following:
xcelium> describe a_b a_b........analog net (electrical ) = 0
Unfortunately, this approach is sometimes ambiguous. For example, consider the following code:
electrical a, b, a_b ; // Defines 3 nets, including a node named a_b V(a,b) <+ 2 * I(a,b) ; // An unnamed branch across a and b
Now, using the command describe a_b is ambiguous, because a_b could refer to the node a_b or to the unnamed branch. To resolve this ambiguity, Tcl assumes that a_b refers to the node and requires you to use a_b_1 to refer to the unnamed branch. So you might have commands and responses like the following:
xcelium> describe a_b a_b........analog net (electrical ) = 0 xcelium> describe a_b_1 a_b_1......branch(a,b) = 0
It might sometimes be necessary to use additional generated names, such as a_b_2, if the names that would otherwise be used, such as a_b_1, are already in use. Generated names are used only for branches, never for nets.
To avoid the problem of ambiguous references, Cadence recommends that you declare and use named branches.