Product Documentation
Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Product Version 22.09, September 2022

Appendix C: Source Protection

Encryption allows you to protect your proprietary parameters, subcircuits, models, and netlists, and release your libraries to your customers without revealing sensitive information. Your customers can run simulations in the Spectre® circuit simulator with the encrypted netlists – the Spectre circuit simulator does not print any data inside the encrypted blocks. Messages about the encrypted portions of your circuit are suppressed.

Spectre AMS Designer simulator uses two different methods to protect (encrypt) source code, depending on what language you use. These two methods are similar but differ in terms of the commands you use and in the way they are implemented.

Language

Method for Protection

Verilog-A, Verilog-AMS, Verilog (digital), VHDL-AMS, and VHDL (digital) code

xmprotect

Spectre code

spectre_encrypt

You cannot probe any nets that go through an encrypted design unit.

You can use source protection with the AMS Designer simulator and analog solver configuration, Spectre solver using the simulation front end (SFE) parser.

Verilog-AMS Protection

It is not possible to partially protect a purely behavioral Verilog-AMS module or a Verilog-AMS module that contains both structural and behavioral information--if you protect anything in such a module, the entire module is protected. However, it remains possible to use Tcl or VPI to create a probe or to access values in the regions of the module that are not explicitly protected.

Protection Guidelines for Automatically Inserted Connect Modules

Automatically-inserted connect modules (AICMs) behave as follows:

Forced Use of CMI 3.0

You can use only a CMI 3.0 device library or a device library compatible with CMI 3.0 in conjunction with source protection. Using an incompatible library in conjunction with source protection causes the simulator to stop immediately during initialization.

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