Special typographical conventions are used to distinguish certain kinds of text in this document. The formal syntax used in this reference uses the definition operator, ::= , to define the more complex elements of the Verilog-AMS language in terms of less complex elements.
- Lowercase words represent syntactic categories. For example,
module_declarationSome names begin with a part that indicates how the name is used. For example,
node_identifierrepresents an identifier that is used to declare or reference a node.
- Boldface words represent elements of the syntax that must be used exactly as presented (except as noted below). Such items include keywords, operators, and punctuation marks. For example,
endmodule
- The shortest permitted abbreviation is shown by capital letters but you can use either upper or lowercase letters in your code. For example, the syntax
-CHecktasks
means that you can type the option as-checktasks,-CHECKTASKS,-ch,-CH,-cH, and so on.
- Vertical bars indicate alternatives. You can choose to use any one of the items separated by the bars. For example,
attribute ::=
abstol
| access
| ddt_nature
| idt_nature
| units
| huge
| blowup
| identifier
- Square brackets enclose optional items. For example,
input declaration ::=
input [ range ] list_of_port_identifiers ;
- Braces enclose an item that can be repeated zero or more times. For example,
list_of_ports ::=
( port { , port } )
- Code examples are displayed in constant-width font.
/* This is an example of the font used for code.*/
- Variables are in italic font, like this: allowed_errors
.
- Keywords, filenames, names of natures, and names of disciplines are set in constant-width font, like this:
keyword,file_name,name_of_nature,name_of_discipline.
-
If a statement is too long to fit on one line, the remainder of the statement is indented on the next line, like this:
qgf = width*length*cfbb*(vgfs - wkf - qb/(2*cbb) -
(vgbs - vfbb + qb/(2*cob))) + qgf_par ;