Feature-Specific License Checkout Order
The following table lists the default license checkout order for different mixed-signal .
|
Feature
|
Default License Checkout Order
|
|---|
|
Verilog-AMS, or Verilog, or VHDL or VHDL-AMS design
|
- Spectre AMS Designer
- 2 MMSIM tokens
- Spectre AMS Connector + Xcelium Single Core
- 1 MMSIM token + Xcelium Single Core
- Spectre AMS Connector + Xcelium Multi Core
- 1 MMSIM token + Xcelium Multi Core
|
|
Verilog-AMS, or Verilog, or VHDL or VHDL-AMS design + WREAL
|
-
Spectre AMS Designer
-
2 MMSIM tokens
-
Spectre AMS Connector + Xcelium Limited
-
1xMMSIM + Xcelium Limited
-
Spectre AMS Connector + Xcelium Single Core
-
1 MMSIM token + Xcelium Single Core
-
Spectre AMS Connector + Xcelium Multi Core
-
1 MMSIM token + Xcelium Multi Core
|
|
Verilog-AMS, or Verilog, or VHDL, or VHDL-AMS design + SVRNM
|
-
Spectre AMS Designer + Xcelium Mixed-Signal App
-
2 MMSIM tokens + Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Limited +Xcelium Mixed-Signal App
-
1xMMSIM + Xcelium Limited + Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Single Core + Xcelium Mixed-Signal App
-
1 MMSIM token + Xcelium Single Core + Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Multi Core + Xcelium Mixed-Signal App
-
1 MMSIM token + Xcelium Multi Core + Xcelium Mixed-Signal App
|
|
Verilog-AMS, or Verilog, or VHDL, or VHDL-AMS design + SVRNM + SVA
|
- Spectre AMS Designer + Xcelium Mixed-Signal App
-
2xMMSIM + Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Limited +Xcelium Mixed-Signal App
-
1xMMSIM + Xcelium Limited + Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Single Core + Xcelium Mixed-Signal App
-
1xMMSIM + Xcelium Single Core+ Xcelium Mixed-Signal App
-
Spectre AMS Connector + Xcelium Multi Core + Xcelium Mixed-Signal App
-
1xMMSIM + Xcelium Multi Core + Xcelium Mixed-Signal App
|
|
Verilog-AMS, or Verilog, or VHDL, or VHDL-AMS design + UVM/SVTB
|
- Spectre AMS Connector + Xcelium Single Core + Xcelium Mixed-Signal App
- 1 MMSIM token + Xcelium Single Core + Xcelium Mixed-Signal App
- Spectre AMS Connector + Xcelium Multi Core + Xcelium Mixed-Signal App
- 1 MMSIM token + Xcelium Multi Core + Xcelium Mixed-Signal App
|
|
Verilog-AMS or Verilog, or VHDL or VHDL-AMS design +UVM/SVTB + SVRNM
|
- Spectre AMS Connector+ Xcelium Single Core + Xcelium Mixed-Signal App
- 1 MMSIM token + Xcelium Single Core + Xcelium Mixed-Signal App
- Spectre AMS Connector + Xcelium Multi Core + Xcelium Mixed-Signal App
- 1 MMSIM token + Xcelium Multi Core+ Xcelium Mixed-Signal App
|
|
Digital (Verilog/VHDL) + SVRNM
|
- Xcelium Limited + Xcelium Mixed-Signal App
- Xcelium Single Core + Xcelium Mixed-Signal App
- Spectre AMS Designer + Xcelium Mixed-Signal App
- 2 MMSIM tokens + Xcelium Mixed-Signal App
- Xcelium Multi Core + Xcelium Mixed-Signal App
|
|
Digital (SystemVerilog) + SVRNM
|
- Xcelium Limited + Xcelium Mixed-Signal App
- Xcelium Single Core + Xcelium Mixed-Signal App
- Xcelium Multi Core + Xcelium Mixed-Signal App
|
|
Digital (Verilog/VHDL, SystemVerilog Design or SVA) + WREAL
|
- Spectre AMS Designer
- 2 MMSIM tokens
- Xcelium Limited + Xcelium Mixed-Signal App
- Xcelium Limited + Spectre AMS Connector
- Xcelium Limited + 1xMMSIM
- Xcelium Single Core + Xcelium Mixed-Signal App
- Xcelium Single Core + Spectre AMS Connector
- Xcelium Single Core + 1 MMSIM token
- Xcelium Multi Core + Xcelium Mixed-Signal App
- Xcelium Multi Core + Spectre AMS Connector
- Xcelium Multi Core + 1 MMSIM token
|
|
Digital (SystemVerilog Testbench)+ WREAL
|
- Xcelium Single Core + Xcelium Mixed-Signal App
- Xcelium Multi Core + Xcelium Mixed-Signal App
|
