You can enable real number modeling in SystemVerilog designs using one of the following:
- Built-in nettypes with real data type and built-in resolution functions, equivalent to the wreal resolution functions
- User-defined nettype (UDN) and resolution function
To declare a nettype use the keyword nettype, and include a data type and optionally a resolution function. It can carry one or more values over a single net. A real value can be used to communicate voltage, current and other values between design blocks. You can also define a user-defined type (UDT), user-defined nettype (UDN), and user-defined resolution function (UDR).
Syntax:
nettype UDT UDN [ with UDR ];
Where,
UDTis the datatypeUDNis the nettype identifiedUDRis the resolution function
UDNs are SystemVerilog structures with a defined resolution function. Nets are used for structural connections and allow for the resolution of multiple drivers. Nets have a single, resolved value based on one or more drivers. Nettypes can only be driven through a continuous assignment, where each assignment represents a driver on the net. A nettype construct can carry one or more values over a single net. A real value can be used to communicate voltage, current, and other quantities between design blocks.
Resolution functions are used to determine the final value of a nettype. The return value of a resolution function is the nettype’s datatype. It is called whenever there is a change on one or more drivers to a net. Nettypes that are defined to only have a single driver do not need to be defined with a resolution function. However, a nettype with a resolution function that has only one driver can still call that resolution function when a driver changes. Also, you can use a resolution function with a single-driver nettype. The resolution function can be used to define monitoring functionality and debug operations on the net.