Real-Number Modeling (RNM) using the SystemVerilog language in a mixed approach borrowing concepts from the digital and analog domains that enables high-performance digital-centric, mixed-signal verification. You can use SV-RNM for the creation of accurate, high-speed Digital Mixed-Signal (DMS) models.
SystemVerilog Real Number Modeling uses real number ports defined in IEEE 1800-2012 standard supporting nettypes (built-in, UDT, UDR, and UDNs) and interconnects. Also, Cadence® provides a EE_pkg package that defines nettype, EEnet to describe analog impedance-based interactions between blocks in a SystemVerilog DMS environment. You can then examine advanced RNM features, SV port connections, and Connect Modules (CM) for AMS interactions.