System Verilog and Verilog-AMS constructs can be used with the SystemVerilog AMS (SVAMS) Parser, which is now integrated with the native verilog (xmvlog) parser. This means that UDN-to-UDN, UDN-to-logic, UDN-to-electrical, UDN-to-Wreal connect modules can be parsed using the xmvlog parser. Dynamic Voltage Supply (DVS) features (the $real_net_alias system task) can also be parsed using the xmvlog parser.
This allows you to create SVAMS connect modules with a more extended set of SystemVerilog and Cadence language constructs.
The following are the unsupported use cases of SVAMS parser:
- Verilog-AMS logic, Verilog-AMS wreal
- Connections with variable ports such as real vars, structs types
- Connections with datatypes UDT-Struct, union, enum
- Generation block inside SVAMS connect modules
- System Verilog assertions and PSL's assertions are not allowed
- SystemVerilog testbench constructs such as interface, program, checker, modports, clocking blocks, module/endmodule
- Using the Verilog-AMS table_model function is not supported
- SVAMS constructs such as initial_step, final_step, and bound_step are not supported for UDN-to-logic, UDN-to-real, and UDN-to-UDN connections
- Using analog constructs (electrical) in UDN-UDN, UDN-logic, UDN-wreal connect modules
- Importing DPI functions