Variable To Wire (VTW) Optimization in Mixed-Signal Designs

For designs having mixed signal nets, you can enable Variable to Wire (VTW) optimization using the -dms_perf option.

The tool analyzes whether a logic or reg data type can be safely treated as a wire. If so, it converts the logic/reg variable to a wire. VTW is enabled inside digital module and disabled at boundary with AMS and DMS connection.

For mixed signal designs, if discipline resolution or coercion happens in a particular connection, VTW optimization is turned off for that particular connection. Logic/Reg assigned in a procedural block (initial/always) is not converted to the wire.

The following example illustrates that with the -dms_perf option specified, top.VOUT_VEC is converted to wire.

rnm_coerce off". xrun top.sv -rnm_coerce off -dms_perf
-----------------------------------------------------
//top.sv
module top ();
reg VOUT_VEC[0:1];
ldo_monitor x1 (VOUT_VEC);
endmodule

module ldo_monitor (clk);
input wire clk[0:1];
endmodule

The following example illustrates that though -dms_perf is specified, top.VOUT_VEC is not converted to wire because it is connected to wrealsum.

xrun top.sv -rnm_tech -dms_perf
-----------------------------------------------------
import cds_rnm_pkg::*;
module top ();
reg VOUT_VEC;

ldo_monitor x1 (VOUT_VEC);
endmodule

module ldo_monitor (clk);
input wrealsum clk;
endmodule