The VHDL-D and SPICE blocks in a design are connected together using a Conversion Element (CE). CE optimization is a process to ensure that minimum number of CEs are required for a given hierarchical or local net that connects one or more SPICE blocks in a design. All unnecessary CEs in the design are eliminated to optimize the design performance.
The VHDL-SPICE CE optimization is performed in the scenarios discussed below as follows:
- A single SPICE block is connected to a VHDL-D signal that is not read by or written to by any other VHDL-D signal
In such a scenario, remove the CE from the SPICE block. The connected VHDL-D signal is treated as analog for computation purpose. - Two or more SPICE blocks are connected to each other through a VHDL-D net (either hierarchical or local) that is not read by or written to by any other VHDL-D signal
In such a scenario, remove the CEs from all the SPICE blocks. The VHDL-D interconnect is treated as analog for computation purpose. - Two or more SPICE blocks are connected to each other through a VHDL-D net (either hierarchical or local) that is read by or written to by other VHDL-D signals
In such a scenario, consider the following cases for each net connection:- If the direction of all SPICE ports connected to the VHDL-D net is the same, keep any one of the CEs and ignore all others. This ensures that there is only one CE between all the SPICE blocks and the VHDL-D signals.
- If the directions of the SPICE ports connected to the VHDL-D net are different, then traverse through all the VHDL-D signals connected to the VHDL-D net and perform one of the following actions:
- If all VHDL-D signals have the direction
IN, keep only oneA2DCE and ignore all others.
- If all VHDL-D signals have the direction
- If all VHDL-D signals have the direction
OUT, keep only oneD2ACE and ignore all others.
- If all VHDL-D signals have the direction
- If VHDL-D signals are all
INOUTsor have different directions, an error message is displayed.
- If VHDL-D signals are all