The Verilog-AMS based real number modeling (RNM) solution facilitates high performance and reasonably accurate modeling of analog behavior to aid verification of mixed-signal designs. You can use disciplineless wreal nets to resolve multiple drivers on wreal signals to suit the expected changes in SV.
To accomplish this, use the six new disciplineless wreal net types--wrealavg, wrealsum, wrealmax, wrealmin, wreal1driver, and wreal4state--added to Verilog-AMS. These disciplineless wreal nettypes enable you to write wreal models that align with the SV-RNM requirement.
Example
To declare disciplineless wreal nets that have resolution associated with them, write:
wrealsum wr_sum_1;
wrealavg wr_avg_1;
wrealmin wr_min_1;
Here is a full code example using the new wreal nettypes:
module top(); //new discipline-less with resolution function avg wrealavg real_wire; source1 I12 (real_wire); source2 I22 (real_wire); sink I32(real_wire); endmodule