ce

The ce statement specifies conversion element parameters for VHDL-to-SPICE connections, optionally for a particular design architecture (cell level), or for a specific pin (port level). If you do not specify a cell or a port name, the elaborator applies the parameter settings to all conversion elements globally.

Using a ce statement, you can define and select VHDL conversion elements for VHDL-to-SPICE connections in your design. You can specify the values of various generics in a conversion element to control the accuracy and performance of the inter-kernel value conversions. Optionally, you can define a conversion element for a given scope of the design by specifying a cell name. Alternatively, you can specify a port name to define a conversion element for the specific pin. If you do not specify a cell or a port, the ce statement applies to the entire design.

The syntax for a ce statement is as follows:

ce name=ceName type=sigType [dir=portDir] [cell=archName] [genericmap=value] [cellport=portName] [excludeport=portName] [priority=high|low] [optimize=on|off]

Valid parameter assignments for the ce statement are as follows:

`name`	Conversion element name using one of the following forms: `library. cell` `library. cell :arch` For example: `name=mylib.std_logic2e` `name=mylib.std_logic2e:arch`
`type`	Digital signal type that connects to SPICE; for example: `type=std_logic`
`dir`	(Optional) Direction of the digital port Valid values:
	`in` or `input`	Input port
	`out` or `output`	Output port
	`inout`	Bidirectional port
	Default value: `inout`
`cell`	(Optional) Name of the cell defining the scope of the `ce` statement; for example: `cell=dummy_spice`
`genericmap`	Parameter for overriding generic values in the conversion element; for example: `genericmap="vsup 3.3 vthi 2.2"`
`cellport`	(Optional) Name of the port (or ports) to which the elaborator will apply the parameter settings specified in the `ce` statement; for example: `cellport="vdd2 gnd2"`
`excludeport`	(Optional) Name of the port (or ports) that will not use the parameter settings specified in the `ce` statement; for example: `excludeport="p0 nx"`
`priority`	(Optional) Priority of the conversion element for optimization. This value determines the conversion element to be used for optimization, when there are multiple conversion elements of different signal types. For example: `ce ... type=base priority=low` `ce ... type=derived priority=high` In the above example, if the conversion element optimization process has to choose one of the conversion elements for optimization, it will choose the derived conversion element because it has `high` priority.
`optimize`	(Optional) The global switch to turn off conversion element optimization. Default is `on.` The following statement for the global `ce` card implies that conversion element optimization will be ignored for the entire design. `ce optimize=off` The following statement, on the other hand, implies that optimization will be ignored for scope `nand2` and below only. Conversion element optimization will occur for all other scopes. `ce optimize=off cell=nand2 ...`

For example:

ce name=mylib.std_logic2e genericmap="vsup 2.4 vthi 1.8 vtlo 1.2" cell=dummy_spice type=std_logic dir=input

Here is an example in the context of an amsd block:

amsd{ portmap subckt=mult16x16_spice autobus=yes refformat=vhdl reffile=mult16x16_spice.vhd config cell=mult16x16_spice use=spice ce name=my_ad_lib.std_logic2e dir=input type=std_logic ce name=my_ad_lib.e2std_logic dir=out type=std_logic }