Parameter Assignments

The software uses any parameter assignments you specify to customize the connect rules. Any customizations you specify apply to domainless nets only. Valid parameter=value assignments for the ie statement are as follows:

`vthi`	Voltage value above which the simulator assigns a logical `1.` The simulator determines the default value from the connect rule.
`vtlo`	Voltage value below which the simulator assigns a logical `0.` The simulator determines the default value from the connect rule.
`vx`	Final real number for logical `x.` The simulator determines the default value from the connect rule.
`tr`	Rise time for analog transition, from `vtlo` to `vthi` or `vx.` Default value: 0.2 ns
`rlo`	Output resistance for L2E when digital input is `0.` Default value: 200 Ohms
`rhi`	Output resistance for L2E when digital input is `1.` Default value: 200 Ohms
`rx`	Output resistance for L2E when digital input is `x.` Default value: 40 Ohms
`rz`	Output resistance for L2E when digital input is `z.` Default value: 10M Ohms
`txdel`	Controls the amount of wait time before a digital port is driven to `x` for the connect modules `E2L` , `E2L_2` , `L2E` , `Bidir` , and `Bidir_2.` Measured in nano seconds. Default value: Four times the `tr` parameter. If the `tr` parameter is not specified for the `ie` statement, the simulator uses the default `tr` value 0.2n and calculates the default `txdel` value as 0.8n. Example: `amsd{` `ie vsup=1.8 txdel=0.9n` `}`
`mode`	Specifies the type of connect module insertion in the `ie` card. You can assign two values to this parameter: `merged` - This is the default value. The merged value instructs the elaborator to insert a single merged connectmodule for all the nets that are connected to the same port and require the same connectmodule. `split` - The `split` value instructs the elaborator to insert a separate connectmodule for every net connected to the same port, irrespective of whether or not they require the same connectmodule.
`vpso`	Converts the PSO X state to a user-supplied voltage in AMS-CPF.
`vdelta`	Voltage delta value ranging from 0 to vsup. Default value: `vsup`/`64`
`vtol`	Voltage tolerance value ranging from 0 to vdelta. Default value: `vdelta`/`4`
`vtrlo`	Ratio of low threshold during value conversion. Default value: `vtlo`/`vsup`.
`vtrhi`	Ratio of high threshold during value conversion. Default value: `vtrhi`/`vsup`.
`vrtol`	Ratio of tolerance during value conversion. The default value is vtlo/vsup.
`currentmode`	Enables wreal current mode processing. Default value: `0`
`connrules`	Connect rule to build using the `vsup=supplyValue` you specify. Valid values:
	`basic`	Build the "basic" connect rule
	`full`	Build the "full" connect rule
	`inhconn_full`	Build inheritance-based connect rule. The connect rule defined using the `inhconn_full` argument can inherit supply voltage automatically. The default supply is `cds_globals.\vdd!` and `cds_globals.\vss!` You can use this argument instead of using the `vsup` parameter to specify the supply voltage. However, if both `vsup` and `connrules=inhconn_full` exist in the same `ie` card, an error is reported. For example: `ie vsup=1.8 connrules = inhconn_full`
	`full_fast`	Build the "full-fast" connect rule
	Default Value: `full_fast` Note: You can find the set of connect rule files that Cadence provides--including the " `basic` ", " `full` ", " `inhconnfull` ", and " `full-fast` " connect rules--in `your_install_dir` `/tools/affirma_ams/etc/connect_lib.` See `your_install_dir` `/tools/affirma_ams/etc/connect_lib/README` for detailed information about them.
`discipline`	Used as the discipline name corresponding to the `ie` card. If this parameter is not specified, the discipline name is auto-generated. In the example below, the discipline name corresponding to the `ie` card in the first `ie` statement will be `logic1_8` instead of the auto-generated discipline name `ddiscrete_1_8.` However, because the `discipline` parameter is not used with the second and third `ie` statements, the corresponding discipline names for these `ie` cards will be `ddiscrete_3_3` and `ddiscrete_4_5.` `amsd{ ie vsup=1.8 discipline=logic1_8 rx=25 ie vsup=3.3 rlo=125 ie vsup=4.5 tr=0.4n }` Important: The `discipline` parameter can take only discrete discipline values. In the example below, the discipline value is not discrete and therefore it is not supported. `ie vsup=1.8 instport="top.sub.pin" discipline="electrical"` For continuous disciplines, use the elaboration `-setdiscipline` option instead. For example: `-setdiscipline "instterm-top.sub.pin- electrical"` Note: Unlike in a connectmap card, the `discipline` parameter in an `ie` card can accept only a single discipline value.
`enable_highz`	If set to `1`, converts HighZ state reported by the Spectre dyn_highz check at the analog (SPICE) port to logic Z at digital (Verilog) port of AMS connect modules. This parameter is supported only by the AMSD built-in default connect rules (full_fast) on electrical-to-logic and bidirectional conversion. Possible values are `0` and 1. The default value is `0.` Note: Conversion of HighZ state results in delay of one transient step. Example: `ie vsup=1.8 enable_highz=1 net="top.n1 top.n5"` To enable the `ie enable_highz` feature, the AMSD built-in Verilog-AMS connect modules are enhanced with system function `$dyn_highz`, which takes two arguments. The first argument is the analog port of the Verilog-AMS module and the second is to enable the highz conversion. It returns a boolean/integer value, where `1` means high-Z and `0` means non-high-Z. Example: `highzState = $dyn_highz(Ain, enable_highz);`
`nox`	If set to 1, disables converting to logic X when the electrical signal is in between `vthi` and `vtlo` in electrical to logic conversion, for the purpose of simpler and faster verification. Default value: `0`

Examples

In the following example, all digital nets that connect to analog in the top.I3 scope have interface elements with vsup=4.5 and tr=1.2 ; all digital nets that connect to analog in the scope of instance top.I1 of cell mid1 have interface elements with vsup=1.8 ; all other nets use the global value, vsup=5.0 :

amsd{ ... ie vsup=5.0 ie inst=top.I3 vsup=4.5 tr=1.2n ie vsup=1.8 cell=mid1 inst=top.I1 }

Here is an example showing how you can specify more than one instance (scope) to use the same supply voltage:

amsd{ ... ie vsup=4.5 inst="testbench.vlog_buf" ie vsup=4.5 inst="testbench.vlog_buf1" ie vsup=4.5 inst="testbench.vlog_buf2" }

You can also specify more than one instance in a single statement like this:

amsd{ ... ie vsup=4.5 inst="testbench.vlog_buf testbench.vlog_buf1 testbench.vlog_buf2" }

Here is an example showing how you can specify different instances (scopes) to use different supply voltages:

amsd{ ... ie vsup=1.8 inst="testbench.vlog_buf" ie vsup=3.0 inst="testbench.vlog_buf1" ie vsup=4.5 inst="testbench.vlog_buf2" }

The following examples showing how you can specify a supply voltage you want to apply to an instance port, a cell port, a net, or to all domainless nets connected to a cell port:

amsd{ ... ie vsup=1.8 instport="top.I1.in" tr = 0.4n }

amsd{ ... ie vsup=1.8 cellport="mid1.w" vtlo=0.7 vthi=1.5 }

amsd{ ... ie vsup=1.8 net="top.n1" rlo=150 rhi=240 }

amsd{ ...

ie vsup=1.8 cellupport="mid2.w" rx=25 }

Here is an example showing how you can specify more than one scope on a single ie statement:

amsd{ ... ie vsup=1.8 cell="mid" inst="top.I1" cellupport="mid.w" }

Here is an example showing how you can build a set of "full" connect rules using a 1.8 Volt supply value:

amsd{ ie vsup=1.8 connrules="full" }

In the following example, the program applies the same custom discipline to cell mid1 and to instance top.I1 (because the parameter = value assignments in the ie statements are exactly the same):

amsd{ ie vsup=1.8 cell="mid1" tr=0.3n rlo=200 ie vsup=1.8 inst="top.I1" tr=0.3n rlo=200 }

The example below describes a global ie card with the default merged connect module insertion. In addition, it describes a scoped ie card for the divider block, which is parameterized for a split connect module insertion.

ie vsup=1.8ie vsup=3.2 mode=split cell=divider

The example below describes how the new vpso parameter can be used with the ie card to convert the PSO X state to a user-supplied voltage in AMS-CPF.

amsd{
ie vsup=3.3 instport="testbench.vlog_buf.I1.in" vpso=0.1
}

The example below describes how to specify the hierarchical dynamic voltage supply.

module top;

electrical e1, e2, e3;

electrical a11, a10, a21, a20, a3;

foo f1 (e1, a11, a10);

foo f2 (e2, a21, a20);

foo f3 (e3, a3, a3);

initial begin // simulation outputs

#10 $display(V(e1),,V(e2),,V(e3));

#20 $display(V(e1),,V(e2),,V(e3));

end

analog begin // setup supplies

V(a11) <+ 1.8;

V(a10) <+ 0.18;

V(a21) <+ 3.3;

V(a20) <+ 0.33;

end

endmodule

module foo(p, a1, a0);

output p, a1, a0;

electrical a1, a0; // local supplies

assign #20 p = 1;

endmodule

//amsd block

ie vddnet=a1 vssnet=a0 inst="top.f1 top.f2" // hierarchical DVS

ie vddnet=top.a21 vssnet=top.a10 inst=top.f3 // normal DVS

//command line

xrun top.vams sim.scs -ieinfo -hier_dvs

Note that hierarchical dynamic voltage supply works for a single identifier (not OOMR style) used in vddnet/vssnet, like a1/a0 in the above example.

When the simulation is run, the tool will insert three IEs:

top.e3__L2E_2_dynsup__ddiscrete_dynsup_full_fast_ie2 for the second IE card, as normal DVS

top.e2__L2E_2_dynsup__ddiscrete_dynsup_full_fast for the first IE card (Hierarchical DVS)

top.e1__L2E_2_dynsup__ddiscrete_dynsup_full_fast for the first IE card

The simulation result would be as follows:

0.18 0.33 0.18

1.8 3.3 3.3

Parameter Assignments

Examples

Related Topics