Product Documentation
Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Product Version 22.09, September 2022

drivers Command Report Format

The drivers command supports two report formats based on the following:

Verilog Signals

The drivers report for digital Verilog-AMS signals is as follows:

value <- ( scope ) verilog_source_line_of_the_driver

For example:

af.........wire (wire/tri) = St1
    St1 <- (board.counter) assign altFifteen = &value

Instead of verilog_source_line_of_the_driver, the following is output when the actual driver is from a VHDL model:

port 'port_name' in module_name [File:
    path_to_file_containing_module], driven by a VHDL model.

This report indicates that the signal is ultimately driven by a port (connected to port_name of the specified module) on a module whose body is an imported VHDL model. The module_name corresponds to the module name of the shell being used to import the VHDL model.

VHDL Signals

The drivers report for VHDL signals is as follows:

description_of_signal = value
     value_contributed_by_driver <- ( scope_name ) source_description

The source_description for the various kinds of drivers are shown below:

A process

Nothing is generated for the source_description. This implies that a sequential signal assignment statement within a process is the driver. The scope_name is the scope name of the process.
Concurrent signal assignment/concurrent procedure call

The source_description is the VHDL source text of the concurrent signal assignment statement or concurrent procedure call that results in a driving value. This concurrent statement is within the scope scope_name.
No drivers

If the signal has no drivers, the text No drivers appears verbatim.
A Verilog driver

If the driver is from a Verilog model, the report has the following form:

port 'port_name' in entity(arch) [File:
    path_to_file_containing_entity], driven by a Verilog model.

This report indicates that the signal is ultimately driven by a port (connected to port_name of the specified entity-architecture pair) on an entity whose body is an imported Verilog model.
Driver from a C model

If the driver is from an imported C model, the report has the following form:

port 'port_name' in entity(arch) [File:
    path_to_file_containing_entity], driven by a C model.
Driver from a LMC model

If the driver is from an imported LMC model, the report has the following form:

port 'port_name' in entity ( arch ) [File:
    path_to_file_containing_entity], driven by a LMC model.
Driver from an OMI model

If the driver is from an imported OMI model, the report has the following form:

port 'port_name' in entity(arch) [File:
    path_to_shell_file], driven by a OMI model.
Resolution/type conversion function in non-verbose Mode

If you do not use the -verbose option, the text [verbose report available ....] may appear. This indicates that the signal gets its value from a resolution function or a type conversion function. Use -verbose to display more information on the derivation of the signal's value.

On the next line of output (indented), a nonverbose driver report is displayed for each signal whose driver contributes to the value of the signal in question.
Resolution function

The following text is generated only when the -verbose option is used:

[resolution function function_name()]

This means that the signal is resolved with the named resolution function. A verbose drivers report is displayed (indented) for all inputs to the resolution function.
Type conversion on formal of port association

The following text is generated only when the -verbose option is used:

[type conversion function function_name(formal)]

This means that the signal's driving value comes from a type conversion function on a formal in a port association. A verbose drivers report is displayed (indented) for the formal port that is the input to the function.
Type conversion on actual of port association

The following text is generated only when the -verbose option is used:

[type conversion function function_name(actual)]

This means that the signal's effective value comes from a type conversion function on an actual in a port association. A verbose drivers report is displayed (indented) for the actual that is the input to the function.
Implicit guard signal

The following text is displayed in response to a query on a signal whose value is computed from a GUARD expression:

[implicit guard signal]
Signal attribute

The following is displayed in response to a query on an IN port that ultimately is associated with a signal valued attribute:

[attribute of signal full_path_of_the_signal]

The full_path_of_the_signal corresponds to the complete hierarchical path of the signal whose attribute is the driver.
Constant expression on a port association

The following is displayed when the value of the signal in question is from a constant expression in a port map association:

[constant expression associated with port port_name]
Composite signals

For a composite signal, a separate report is displayed for each group of subelements that can be uniquely named and that have the same set of drivers.


Related Topic



 ⠀
X