drivers

Displays a list of all contributors to the value of the specified digital objects.

You can use the scope -drivers [ scope_name ] command to display the drivers of each digital object that is declared within a specified scope. See scope.

For Verilog, the drivers command cannot find the drivers of a wire or register unless the object has read and connectivity access. However, even if you have specified access to an object, its drivers might have been collapsed, combined, or optimized away. In this case, the output of the command might indicate that the object has no drivers. For details on specifying access to simulation objects, see Access to Digital Simulation Objects.

When the simulator is stopped in a resolution function (at_resfunc), the TCL drivers command can be invoked without arguments. See at_resfunc.

The drivers command is supported on user-defined nettypes. For more information on user-defined nettypes, refer to User-Defined Nettype and Resolution Function.

drivers Command Syntax

drivers
   [-show] object_name...
     [-effective]
     [-future]
     [-novalue]
     [-verbose]

drivers Command Options

This section describes the options that you can use with the Tcl drivers command.

drivers Command Examples

The following examples illustrate use cases for the drivers command:

• Output for Digital Verilog-AMS Signals
• Output for VHDL Signals

Output for Digital Verilog-AMS Signals

The following command lists the drivers of a signal called f.

xcelium> drivers f
f..........wire (wire/tri) = StX
    StX <- (board.counter) assign fifteen = value[0] & value[1] &
              value[2] & value[3]

The following command lists the drivers of two signals called f and af.

xcelium> drivers f af
f..........wire (wire/tri) = StX
    StX <- (board.counter) assign fifteen = value[0] & value[1] &
              value[2] & value[3]
af.........wire (wire/tri) = StX
    StX <- (board.counter) assign altFifteen = &value

The following command lists the drivers of a signal called top.under_test.sum.

xcelium> drivers top.under_test.sum
top.under_test.sum...output [1:0] (wire/tri) = 2'h0 (-W)
    2'h0 <- (top.under_test) assign {c_out, sum} = a + b + c_in

The following command lists the drivers of a signal called board.count.

xcelium> drivers board.count

board.count......wire [3:0]
    count[3] (wire/tri) = St1 
        St1 <- (board.counter.d) output port 1, bit 0 (.counter.v:10)
    count[2] (wire/tri) = St0
         St0 <- (board.counter.c) output port 1, bit 0 (./counter.v:9)
    count[1] (wire/tri) = St1
         St1 <- (board.counter.b) output port 1, bit 0 (./counter.v:8)
    count[0] (wire/tri) = St0
         St0 <- (board.counter.a) output port 1, bit 0 (./counter.v:7)

The following commands list the drivers of a mixed bus w.

xcelium> drivers w
xmsim: *E,MIXBOFF: Mixed discipline bus 'w' needs an index.
xcelium> drivers w[0]
xmsim: *E,TNODIA: No drivers exist for analog object: top.w[0].
xcelium> drivers w[1]
w..........wire [0:2]
w[1] (wire/tri) = StX
No drivers
xcelium> drivers w[2]
w..........wire [0:2]
w[2] (wire/tri) = StX
No drivers

The following command shows the error message that the simulator displays if you run the xmsim simulator in regression mode and then use the drivers command to find the drivers of an object that does not have read and connectivity access.

xcelium> drivers count
xmsim: *E,OBJACC: Object must have read and connectivity access:
                   board.count.

The following examples illustrates the output of the drivers command when the actual driver is from a VHDL model:

xcelium> drivers :u1.a

u1.a.......input (wire/tri) = St1
    St1 <- (:u1) driven by a VHDL model

xcelium> drivers :u1.v.d

u1.v.d.....input (wire/tri) = St1
    St1 <- (:u1) port 'a' in module 'and2' [File: ./verilog.v],
         driven by a VHDL model

xcelium>

This report indicates that the signal :u1.v.d is ultimately driven by a port (connected to port a of the module and2) on a module whose body is an imported VHDL model.

Drivers within the scope of automatically inserted connect modules are listed by giving the automatically inserted module name only. The verilog_source_line_of_the_driver does not list the source line. For example:

xcelium> drivers result
result.....input (wire/tri) = StX
  StX <- (top.analogResultelect_to_logiclogic) module top

where top.analogResultelect_to_logiclogic is the auto-generated instance name for an auto-inserted connect module

Output for VHDL Signals

The following examples use the VHDL model shown in the "drivers.vhd" section of the "Code Examples" appendix in Cadence Verilog Simulation User Guide. A run command has been issued after invoking the simulator.

The following command shows the drivers of signal s. The string [verbose report available .....] indicates that type conversion functions or resolution functions are part of the hierarchy of drivers. Use the -verbose option to display this additional information.

xcelium> drivers s
s..........signal : std_logic = '0'
    [verbose report available.....]
    '0' <- (:GATE:p)
    '0' <- (:) s <= '0' after 1 ns

The following command includes the -novalue option, which suppresses the display of the current value of each driver.

xcelium> drivers s -novalue

s..........signal : std_logic
    [verbose report available.....]
    (:GATE:p)
    (:) s <= '0' after 1 ns

The following command includes the -verbose option, which causes the inclusion of resolution function and type conversion function information. This report shows that the port :GATE:q is one of the contributing drivers, and that there is a type conversion function bit_to_std through which the port's value is routed before being assigned to the signal :s. The report also shows that there is a concurrent signal assignment statement contributing as one of the sources to the resolution function.

xcelium> drivers s -verbose
s..........signal : std_logic = '0'
    '0' <-[resolution function @ieee.std_logic_1164:resolved()]
         <src 1>
              '0' <- (:GATE) [type conversion function
                   bit_to_std(<formal>)]
              <formal> connected to port q

                   :GATE:q....port : inout BIT = '1'
                   '0' <- (:GATE:p)
         <src 2>
              '0' <- (:) s <= '0' after 1 ns

The following command shows the drivers :gate:q.

xcelium> drivers :gate:q
GATE:q.....port : inout BIT = '1'
    '0' <- (:GATE:p)

The following command includes the -effective option, which displays contributions to the effective value of the signal instead of to the driving value.

xcelium> drivers :GATE:q -effective

GATE:q.....port : inout BIT = '1'
    [verbose report available.....]
    '0' <- (:GATE:p)
    '0' <- (:) s <= '0' after 1 ns

The following command includes the -verbose option, which helps you to understand where the effective value of 1 in the previous example comes from.

xcelium> drivers :GATE:q -effective -verbose

GATE:q.....port : inout BIT = '1'
    '1' <- (:GATE) [type conversion function std_to_bit(<actual>)]
    <actual> connected to signal s

         :s.........signal : std_logic = '0'
         '0' <-[resolution function @ieee.std_logic_1164:resolved()]
              <src 1>
                   '0' <- (:GATE) [type conversion function 
                            bit_to_std(<formal>)]
                   <formal> connected to port q  
                      :GATE:q....port : inout BIT = '1'
                        '0' <- (:GATE:p)
              <src 2> 
                  '0' <- (:) s <= '0' after 1 ns

The following command shows the output of the drivers command when the driver is from a Verilog model.

xcelium> drivers -effective i1:a
i1:a.......port : in std_logic = '1'
    '1' <- (and2_top.i1) driven by a Verilog model

xcelium> drivers -effective i1:i1:port1
i1:i1:port1...port : in std_logic = '1'
    '1' <- (and2_top.i1) port 'a' in and2(and2_bot) [File:
         ./and2.vhd], driven by a Verilog model

Related Topic

• drivers Command Report Format