The Tcl reset command resets the currently loaded model to its original state at time zero. The time-zero snapshot, created by the elaborator, must still be available.
The reset command is supported only for pure digital designs and cannot be used for mixed-signal designs.
The Tcl debug environment remains the same as much as possible after a reset.
- Tcl variables remain as they were before the reset.
-
SHM and VCD databases remain open, and probes remain set.
VCD databases created with the
$dumpvarscall in Verilog source code are closed when you reset. - Breakpoints remain set.
- Watch Windows and the SimVision waveform viewer window remain the same.
Forces and deposits in effect at the time you issue the reset command are removed.
reset Command Syntax
reset
reset Command Options
None.
reset Command Example
The following command resets the currently loaded model to its original state at time zero. The snapshot created at time zero must still be available.
xcelium> reset
This command does not work on mixed-signal designs. The following example shows what happens if you try to reset a mixed-signal design.
xcelium> reset *E,RESTAG: Reset not supported for mixed-signal designs.