scope

Lets you

• Set the current debug scope (-set)

• List the automatically-inserted connect module instances within a scope or branch of the design hierarchy (-aicms)

• Describe items declared within a scope (-describe)

• Display the drivers of digital objects declared within a scope (-drivers)

• List the resolved disciplines of all nets within a scope or branch of the design hierarchy (-disciplines)

• Print the source code, or part of the source code, for a scope (-list)

• Display scope information (-show)

See the "Traversing the Model Hierarchy" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information.

scope Command Syntax

scope [-set] [scope_name]
      -up
      -aicms [scope_spec]
          -recurse
          -all
      -describe [scope_name]
          -names
          -sort {name|kind|declaration}
      -drivers [scope_name]
      -disciplines [scope_spec]
          -recurse
          -all
          -sort {name|kind|declaration}
      -list [line|start_line end_line] [scope_name]
      -show

scope Command Options

This section describes the options that you can use with the Tcl scope command.

scope Command Example

The following example prints the name of the current scope. The -set modifier is not required.

xcelium> scope -set

The following example sets the debug scope to scope u1. The -set modifier is not required.

xcelium> scope -set u1

The following example moves the debug scope up one level in the hierarchy.

xcelium> scope -up

For the next example, you have a design that contains a top level module (top) in which three connect_module instances are instantiated with a merged connect mode attribute.

The command

xcelium> scope -aicms -all -recurse

lists all automatically-inserted connect module (AICM) instances in the design as follows.

top.connect5a__elect_to_logic__logic (merged) is:
    instance of connect_module:     elect_to_logic,
    inserted across signal:         top.connect5a,
    and ports of discipline:        logic.
top.connect0a__elect_to_logic__logic (merged) is:
    instance of connect_module:     elect_to_logic,
    inserted across signal:         top.connect0a,
    and ports of discipline:        logic.
top.connect2a__elect_to_logic__logic (merged) is:
    instance of connect_module:     elect_to_logic,
    inserted across signal:         top.connect2a,
    and ports of discipline:        logic.

The following example shows the output of a similar design, in which the value of the connect mode attribute is split.

xcelium> scope -aicms -all -recurse

top.connect5a__dig5__in (split) is instance of connect_module elect_to_logic:
    connected where signal:         top.connect5a,
    joins port:                     in,
    of instance:                    dig5.
top.connect5a__dig6__in (split) is instance of connect_module elect_to_logic:
    connected where signal:         top.connect5a,
    joins port:                     in,
    of instance:                    dig6.
top.connect0a__dig0__in (split) is instance of connect_module elect_to_logic:
    connected where signal:         top.connect0a,
    joins port:                     in,
    of instance:                    dig0.
top.connect0a__dig1__in (split) is instance of connect_module elect_to_logic:
    connected where signal:         top.connect0a,
    joins port:                     in,
    of instance:                    dig1.

The following example illustrates how to display a list of resolved disciplines.

xcelium> scope -discipline -recurse
net disciplines for: top.I3 (sareg)

result.....input (logic)
clkSig.....input (unknown discipline)
trigger....input (unknown discipline)

net disciplines for: top.I4 (daconv)

compSig....output (electrical)
b0.........input (logic)
b1.........input (logic)
b2.........input (logic)
b3.........input (logic)
b4.........input (logic)
b5.........input (logic)
b6.........input (logic)
b7.........input (logic)

net disciplines for: top.I0 (signalSrc)

gnd........analog net (electrical)
sig........output (electrical)

net disciplines for: top.I2 (comparator)

inn........input (electrical)
inp........input (electrical)
net55......wire (electrical)
net79......wire (electrical)
net84......wire (electrical)
net92......wire (electrical)
net94......wire (electrical)
out........output (electrical)
vref1......wire (electrical)

net disciplines for: top.I1 (samplehold)

gnd........analog net (electrical)
holdSig....output (electrical)
inSig......input (electrical)
trigger....input (unknown discipline)

net disciplines for: top.compOut__elect_to_logic__logic (elect_to_logic)

aVal.......input (electrical)
dVal.......output (logic)

The following command displays the disciplines of nets and buses, one of which is a mixed bus.

xcelium> scope -discipline
net disciplines for: top (top)
e..........wire (electrical)
d..........wire (unknown discipline)
w..........wire (mixed bus)

The following command displays a list and a description of all objects declared in the current debug scope (a Verilog-AMS module).

xcelium> scope -describe
clr..............register = 1'hx
clk..............register = 1'hx
data.............register [3:0] = 4'hx
q................wire [3:0] (wire/tri) = 4'hx
end_first_pass...named event
h1...............instance of module hardreg
inSig............analog net (electrical) = 3.45
vplus5_ground....branch(vplus5) = 2.22
sig1.............inout (electrical) = 0.12
R1...............instance of 'resistor' Spice primitive
vout_vspply_n....branch(vout,vspply_n) = 0

The following command displays a list and a description of all objects declared in the current debug scope (a VHDL architecture).

xcelium> scope -describe
top..............component instantiation
load_nickels.....process statement
load_dimes.......process statement
load_cans........process statement
load_action......process statement
gen_clk..........process statement
gen_reset........process statement
gen_nickels......process statement
gen_dimes........process statement
gen_quarters.....process statement
$PROCESS_000.....process statement
$PROCESS_001.....process statement
stoppit..........signal : BOOLEAN = TRUE
t_NICKEL_OUT.....signal : std_logic = '0'
t_EMPTY..........signal : std_logic = '1'
t_EXACT_CHANGE...signal : std_logic = '0'
t_TWO_DIME_OUT...signal : std_logic = 'Z'
...

...

t_NICKELS........signal : std_logic_vector(7 downto 0) = "11111111"
t_RESET..........signal : std_logic = '0'

The following command lists the names of all objects declared in the current debug scope. No description is included.

xcelium> scope -describe -names
clr clk data q end_first_pass h1

The following example displays a list and a description of all objects declared in the current debug scope. Objects are listed in alphabetical order.

xcelium> scope -describe -sort name

The following command displays a list and a description of all objects declared in the current debug scope. Objects are sorted by type of declaration.

xcelium> scope -describe -sort kind

The following example displays a list and a description of all objects declared in scope h1. Objects are listed in the order in which they were declared in the source code.

xcelium> scope -describe -sort declaration h1
clk.............input (wire/tri) = StX
clrb............input (wire/tri) = StX
d...............input [3:0] (wire/tri) = 4'hx
compSig.........output (electrical) = 0
q...............output [3:0] (wire/tri) = 4'hx
f1..............instance of module flop
f2..............instance of module flop
f3..............instance of module flop
f4..............instance of module flop
compSig_ground..branch(compSig) = 0

The following command shows the drivers for all objects declared in scope h1.

xcelium> scope -drivers h1

clk........input (wire/tri) = St1
    St1 <- (hardrive.h1) input port 2, bit 0 (./hardrive.v:8)
clrb.......input (wire/tri) = St1
    St1 <- (hardrive.h1) input port 3, bit 0 (./hardrive.v:8)
d..........input [3:0] (wire/tri) = 4'h2
    [3] = St0
         St0 <- (hardrive.h1) input port 1, bit 3 (./hardrive.v:8)
    [2] = St0
         St0 <- (hardrive.h1) input port 1, bit 2 (./hardrive.v:8)
    [1] = St1
         St1 <- (hardrive.h1) input port 1, bit 1 (./hardrive.v:8)
    [0] = St0
         St0 <- (hardrive.h1) input port 1, bit 0 (./hardrive.v:8)
q..........output [3:0] (wire/tri) = 4'h1
    [3] = St0
         St0 <- (hardrive.h1.f4) nd7 (q, e, qb)
    [2] = St0
         St0 <- (hardrive.h1.f3) nd7 (q, e, qb)
    [1] = St0
         St0 <- (hardrive.h1.f2) nd7 (q, e, qb)
    [0] = St1
         St1 <- (hardrive.h1.f1) nd7 (q, e, qb)

In the following example, the design was elaborated using the default access level (no read or write access to simulation objects). Notice the difference in output between this example and the previous example, where the design was elaborated with full access (xmelab -access +r+w). In this example, only the drivers for wires and registers with read access are shown.

xcelium> scope -drivers h1
q..........output [3:0]
    q[3] (wire/tri) = St0
         St0 <- (hardrive.h1.f4) nd7 (q, e, qb)
    q[2] (wire/tri) = St0
         St0 <- (hardrive.h1.f3) nd7 (q, e, qb)
    q[1] (wire/tri) = St0
         St0 <- (hardrive.h1.f2) nd7 (q, e, qb)
    q[0] (wire/tri) = St1
         St1 <- (hardrive.h1.f1) nd7 (q, e, qb)

The following example lists the drivers for a mixed bus.

xcelium> scope -drivers
d..........wire (wire/tri) = StX
No drivers
e..........wire (electrical) = Inf
No drivers
w..........wire [0:2]
w[1] (wire/tri) = StX
No drivers
w..........wire [0:2]
w[2] (wire/tri) = StX
No drivers

The following example lists the source for the current debug scope.

xcelium> scope -list

The following example lists the source for scope u1.

xcelium> scope -list u1

The following example displays line 12 of the source for the current debug scope.

xcelium> scope -list 12

The following example lists lines 10 through 15 of the source for the current debug scope.

xcelium> scope -list 10 15

The following command lists lines from the top of the module through line 10 of the source for the current debug scope.

xcelium> scope -list - 10

The following command lists lines of source for the current debug scope, beginning with line 30.

xcelium> scope -list 30 -

The following command shows the output of the scope -describe command when you run in regression mode and some objects do not have read or write access.

xcelium> scope -describe h1
clk........input (-RW)
clrb.......input (-RW)
d..........input [3:0]
    d[3] (-RW)
    d[2] (-RW)
    d[1] (-RW)
    d[0] (-RW)
q..........output [3:0]
    q[3] (wire/tri) = St0
    q[2] (wire/tri) = St0
    q[1] (wire/tri) = St0
    q[0] (wire/tri) = St1
f1.........instance of module flop
f2.........instance of module flop
f3.........instance of module flop
f4.........instance of module flop

Related Topic

• Enabling Read, Write, or Connectivity Access to Digital Simulation Objects