Creates or operates on a breakpoint. You can
- Create various kinds of breakpoints (using the
-createmodifier followed by an option that specifies the breakpoint type)
- Display information on breakpoints (
-show)
- Disable a breakpoint (
-disable)
- Enable a previously disabled breakpoint (
-enable)
- Delete a breakpoint (
-delete)
See the "Setting Breakpoints" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information:
Syntax
stop
-create -assert [{-all | -depth {levels | all | to_cells}}] [scope_name] -condition {tcl_expression}
-delta delta_cycle_number [-relative|-absolute] [-start delta_cycle_number] [-modulo delta_cycle_number] [-timestep]-iso_rule rule_name [rule_name ...] [-iso_enable | -iso_disable]-label "stop_message"
-line line_number
{-unit unit_name | [ scope_name ] [-all]}
[-file filename]
-object object_names-at_resfunc <net> -cv_limit <num>-pdname power_domain_name [power_domain_name ...][-isolation [-iso_disable | -iso_enable]]
[-pd_off]
[-pd_on]
[-pd_standby]
[-pd_trans]
[-retention [-sr_restore | -sr_save]]
-process process_name
-pwr_mode_transition mode_transition_name [mode_transition_name ...] -randomize [-always] [object_name ] -sr_rule rule_name [rule_name ...] [-sr_save | -sr_restore] -subprogram subprogram_name
-time time_spec [-relative | -absolute] [-start time_spec] [-modulo time_spec]
[-continue] [-delbreak count] [-execute command] [-if { tcl_expression}] [-name break_name] [-silent] [-skip count]
-delete { break_name | pattern} ... -disable { break_name | pattern} ... -enable { break_name | pattern} ... -show [{ break_name | pattern} ...]
The argument to -delete, -disable, -enable, or -show can be
- A break name
- A list of break names
- A pattern
- The asterisk (*) matches any number of characters
- The question mark (?) matches any one character
- [ characters ] matches any one of the characters
- Any combination of literal break names and patterns
Modifiers and Options
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Modifiers |
Options and Arguments |
Function |
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Creates a breakpoint. This modifier must be followed by an option that specifies the breakpoint type:
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-assert [{-all | -depth {levels | all | to_cells}}] [scope_name] |
The Specify how many scope levels to descend when searching for assertions to stop by using
By using the |
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Sets a breakpoint that triggers when any digital object referenced in For RNM nets, you can set condition for Although condition breakpoints are not triggered by changes in analog objects, you can include analog objects in the conditional expression, and their values are used when the condition is evaluated (due to a digital object changing value). The simulator does not support stop points on individual bits of registers. If a bit-select of a register appears in the expression, the simulator stops and evaluates the expression when any bit of that register changes value. The same holds true for compressed wires. See Tcl Expressions as Arguments for details on the format of conditional expressions. Objects included in a |
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Resumes the simulation after executing the breakpoint. The simulator does not go into interactive mode. |
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Deletes the breakpoint after it has triggered |
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Sets a breakpoint that triggers when the simulation delta cycle count reaches the specified delta cycle. The delta cycle specification can be absolute or relative (the default). If absolute, the breakpoint is automatically deleted after the delta cycle is reached and the breakpoint triggers. If relative, the delta cycle specification is an interval, and the breakpoint stops the simulation every Use The
The See the "Setting a Delta Breakpoint" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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Sets a breakpoint when the resolution function value changes for the target user-defined nettype (UDN). The break occurs in the resolution function for any RNM net within the specified scope. Optionally, you can set the breakpoint on the number of convergence iterations using by the When in resolution function, no other additional argument needs to be added to the TCL The |
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-iso_rule
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Stop when the specified isolation rule becomes enabled or disabled. |
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rule_name [rule_name ...] [-iso_enable | -iso_disable]
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You can specify multiple isolation rule names.
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Specify a label for the breakpoint message. The breakpoint will issue the stop_message. For example:
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Executes the specified Tcl command when the breakpoint is triggered. If the command that you want to execute requires an argument, enclose the command and its argument in curly braces. You also can specify that you want to execute a list of commands. Separate the commands with a semicolon. Tcl, however, displays only the output of the last command. |
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Sets a condition on the breakpoint. The breakpoint triggers only if the given Tcl Boolean expression evaluates to true (non-zero, non-x, non-z). This option can be used with any breakpoint type. For more information on the format of For RNM nets, you can set condition for Objects included in an |
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Sets a breakpoint that triggers when the specified line number is about to execute. You can set breakpoints on both analog and digital code statements. You cannot set a line breakpoint when you are using the simulation front end (SFE) parser. In addition, because structural code is not sequential, you cannot set line breakpoints in such code. You must specify which design unit contains the line. There are two ways to do this: Use Specify the name of a particular scope in the design hierarchy. This creates an instance-specific breakpoint. The breakpoint occurs only for that particular instance of the corresponding design unit, no matter where else it may appear in the design hierarchy. To create a breakpoint that is not instance-specific using the |
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The You must compile with the See the "Setting a Source Code Line Breakpoint" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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Specifies a name for the breakpoint. This name can then be used to delete, disable, or enable the breakpoint. If you do not use |
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Sets a breakpoint that triggers when the specified object changes value (wires, signals, registers, and variables) or is written to (memories). Note: You cannot create object breakpoints for analog objects. The object specified as the argument must have read access for the breakpoint to be created. An error is printed if the object does not have read access. See Access to Digital Simulation Objects. See the "Setting an Object Breakpoint" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
-pdname
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Set a breakpoint that triggers when the specified power domain changes status. If no options are |
power_domain_name [power_domain_name ...] [-isolation [-iso_disable | -iso_enable]] [-pd_off] [-pd_on] [-pd_standby] [-pd_trans] [-retention [-sr_restore | -sr_save]] |
The -pdname option has several sub-options that let you create power domain breakpoints that trigger under specific conditions:
This option stops the simulation when the specified power domain has transitioned to the ON state or to the UNINITIALIZED state. The state of the power domain is UNINITIALIZED when the simulation is being controlled by active state conditions, and when the power domain is on but there are no active state conditions enabled to specify the nominal condition to which the domain should transition.
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Sets a breakpoint that triggers when the specified VHDL named process starts executing or when it resumes executing after a wait statement. You must compile with See the "Setting a Process Breakpoint" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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Suppresses the display of the message that is printed when a breakpoint triggers. |
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Tells the simulator to ignore the breakpoint for the first You can use |
-pwr_mode_transition
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mode_transition_name mode_transition_name ...] |
Stop when the specified power mode transition starts and ends. |
-randomize
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Sets a breakpoint in SystemVerilog randomize() method calls. The SystemVerilog built-in randomize() function returns the value 1 for success or 0 for failure. A failure occurs because there are conflicts in the collection of constraints to solve or because a variable is over-constrained. |
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-always] [object_name] |
The You can include an |
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-sr_rule
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Stop when the specified state retention rule saves or restores its variables. | |
rule_name [rule_name ...] [-sr_save | -sr_restore]
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You can specify multiple state retention rule names.
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-subprogram |
Set a breakpoint that triggers when the specified VHDL subprogram or Verilog task or function is |
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subprogram_name
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You must compile with the |
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Sets a breakpoint that triggers at the specified time. The time can be absolute or relative (the default). Absolute time breakpoints are automatically deleted after they trigger. Relative time breakpoints are periodic, stopping, for example, every 10 ns. The digital solver is always active when the simulator stops for a time breakpoint. Use The When you execute a See the "Setting a Time Breakpoint" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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{ |
Disables the breakpoints specified by the argument without deleting them. See the "Disabling, Enabling, Deleting, and Displaying Breakpoints" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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{ |
Enables the previously disabled breakpoints specified by the argument. See the "Disabling, Enabling, Deleting, and Displaying Breakpoints" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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{ |
Deletes the breakpoints specified by the argument. See the "Disabling, Enabling, Deleting, and Displaying Breakpoints" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
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[{ |
Shows the status of the breakpoints specified by the argument. If no breakpoint is specified, all breakpoints are shown. See the "Disabling, Enabling, Deleting, and Displaying Breakpoints" section of the "Debugging Your Design" chapter in Cadence Verilog Simulation User Guide for more information. |
Example
Object Breakpoints
The following command creates a breakpoint that stops simulation when sum changes value. The -create modifier is not required. Because the -name option is not included to specify a breakpoint name, xmsim assigns a sequential number as the name. This breakpoint is called 1.
xcelium> stop -create -object sum Created stop 1
The following command creates a breakpoint named mybreak that stops simulation when sum changes value.
xcelium> stop -object sum -name mybreak Created stop mybreak
The following command creates a breakpoint that stops simulation when EEnet_net1 changes value.
xcelium> stop -object EEnet_net1 Created stop 1 xcelium> run 5 ns 0 FS + 1 (stop 1: top.EEnet_net1 = '{V:4.9505, I:0, R:99.0099})
The following command creates a breakpoint that stops simulation when resolution function value changes. net1 is a user defined nettype that has a user defined resolution function.
xcelium> stop -create -at_resfunc top.net1Created stop 1xcelium> run50 NS + 1 (stop 1: Resolution Function udt_package::Tavg)resolving net: top.net1
The following command creates a breakpoint that triggers when sum changes value. The breakpoint is ignored the first 3 times it triggers.
xcelium> stop -object sum -skip 3
The following command creates a breakpoint that stops simulation when clr changes value. The value data command is executed when the breakpoint triggers. Because the value command requires an argument, it must be enclosed in curly braces.
xcelium> stop -object clr -execute {value data}
The following command creates a breakpoint that triggers when clr changes value. The value data command is executed when the breakpoint triggers. The -continue option prevents the simulator from entering interactive mode every time the stop triggers.
xcelium> stop -object clr -execute {value data} -continue
The following command creates an object breakpoint that triggers when data changes value. The -delbreak option specifies that the breakpoint is deleted after it triggers three times.
xcelium> stop -object data -continue -delbreak 3
The following command creates a breakpoint that triggers when clk changes value, but only if clk is high. See Tcl Expressions as Arguments for details on the syntax of the argument to the -if option.
xcelium> stop -object clk -if {#clk == 1} -continue
The following command creates a breakpoint that triggers when data[1] has the value 1 and the time becomes greater than 3 ns.
stop -object data -if {#data[1] == 1 && [time ns -nounit] > 3}
The following command shows the error message that is displayed if you run in regression mode and then try to set an object breakpoint on an object that does not have read access.
xcelium> stop -object clk| xmsim: *E,RDACRQ: Object does not have read access: hardrive.clk.
The following shows an error caused by trying to create a breakpoint on an analog object.
xcelium> stop -object compSig xcelium: *W,STALOB: Cannot set stop on analog object: top.dac.compSig. This object ignored. xmsim: *E,STOBEX: Object expected after -OBJECT option of stop command.
Line Breakpoints
The following command creates a breakpoint that stops simulation when line number 10 in the current debug scope is about to execute.
xcelium> stop -line 10
The following command creates a breakpoint that stops simulation when line number 13 in scope counter is about to execute.
xcelium> stop -line 13 counter
In the following command, the -all option specifies that the stop is noninstance-specific. The breakpoint occurs on all scopes which are instances of the same module. For example if there are two instances of module m16, as follows:
module board; <declarations>m16 counter1 (...); m16 counter2 (...); <code> endmodule
the breakpoint triggers when line 13 in either counter1 or counter2 is about to execute.
xcelium> stop -line 13 counter1 -all
The following command is equivalent to the command shown in the previous example. Both commands create non-instance-specific breakpoints.
xcelium> stop -line 13 -unit m16
In the following example, the -file option specifies which of the source files that make up the given scope (or the debug scope if none is given) contains the specified line. This is necessary if the scope has multiple source files.
xcelium> stop -line 13 counter -file foo.v
Time Breakpoints
The following command creates a breakpoint that stops simulation at absolute time 200 ns. The breakpoint is automatically deleted after it triggers.
xcelium> stop -time 200 ns -absolute
The following command creates a repetitive breakpoint that stops the simulation every 200 ns and then executes the value command. The -relative option is the default for time breakpoints.
xcelium> stop -time 200 ns -relative -execute {value data}
The following command creates a repetitive breakpoint that stops the simulation every 200 ns. The -start option specifies the absolute time at which the breakpoint starts. For example, if the current simulation time is 300 ns, the breakpoint stops the simulation at time 600, 800, 1000, and so on.
xcelium> stop -time 200 ns -start 600 ns
In the following example, the current simulation time is 300 ns. The absolute time specified with -start is before the current simulation time. The first stop occurs at the next future time at which it would have occurred had the stop been set at the time specified with -start. In this example, the first stop occurs at time 450 ns.
xcelium> stop -time 200 ns -start 250 ns
The following example shows how the -modulo option is used to save a breakpoint pattern. Suppose that you simulate to time 300 ns and then set a repetitive breakpoint with the following command:
xcelium> stop -time 200 ns -start 350 ns
This command stops the simulation at time 350, 550, 750, and so on. If you then execute a save -environment command to save your debug environment, the following line is written to the script:
stop -create -name 1 -time 200 NS -relative -modulo 950 NS
If you then exit and re-enter the simulation and source the script containing this command, the breakpoint pattern is re-established. In this example, if you restart the simulation and start at time 0, the breakpoint triggers the first time at time 150. It then triggers at 350, 550, 750, and so on.
The following command includes the -if option to set a breakpoint at time 100 ns (relative) if data[1] has the value 1.
xcelium> stop -time 100 ns -if {#data[1] == 1}
Delta Breakpoints
The following command creates a breakpoint that stops the simulation when it reaches 20 delta cycles. The breakpoint is automatically deleted after it triggers.
xcelium> stop -delta 20 -absolute
The following command creates a repetitive breakpoint that stops the simulation every 10 delta cycles. The -start option specifies the absolute delta cycle at which the breakpoint starts. For example, if the current delta cycle count is 0, the breakpoint stops the simulation when the delta cycle count is 30, 40, 50, and so on.
xcelium> stop -delta 10 -start 30
Condition Breakpoints
In a condition breakpoint, the argument to the -condition option is a Tcl expression. See Tcl Expressions as Arguments.
The following command sets a condition breakpoint that stops the simulation when count, the output of a 32-bit counter, has the value 100, decimal. The signal count is available from the top level of the hierarchy.
Verilog: xcelium> stop -condition {[value %d top.count] = 100} VHDL: xcelium> stop -condition {[value %d :count] = 100}
If you are currently at the top level, you can omit the hierarchical path specification to count , and the two commands shown in the previous example could be written as follows:
xcelium> stop -condition {[value %d count] = 100}
The value command uses the value of the vlog_format (or vhdl_format) variable. If you set the value of this variable to %d, the command shown in the previous example could be written as follows:
xcelium> stop -condition {[value count] = 100}
Instead of using the value command to get the value of count into the expression evaluator, you can use #count. Include the format specifier after the # sign.
xcelium> stop -condition {#%dcount = 100}
For Verilog, you can use the standard notation (for example 4'b0011). For example, you can set the breakpoint on count as follows:
xcelium> stop -condition {#count = 32'd100} xcelium> stop -condition {#count = 32'b00000000000000000000000001100100}
VHDL does not have the same type of notation. Vectors must be enclosed in quotation marks, as shown in the next example.
xcelium> stop -condition {#count = "00000000000000000000000001100100"}
The following command sets a condition breakpoint that stops the simulation when bit 0 of count is 1. The expression is evaluated when any bit of count changes value. For VHDL, single-bit entities must be enclosed in single quotation marks.
Verilog: xcelium> stop -condition {#count[0] == 1} VHDL: xcelium> stop -condition {#count(0) == `1'}
The following command is identical to the previous command. An explicit value command is used to get the value of count (bit 0) into the expression parser.
Verilog: xcelium> stop -condition {[value %b count[0]] == 1'b1} VHDL: xcelium> stop -condition {[value %b count(0)] == `1'}
In the following command, the -if option is used to conditionalize the condition breakpoint. This breakpoint stops the simulation at the next positive edge of the clock if en1 or en2 is 1.
Verilog: xcelium> stop -condition {#clock == 1} -if {#en1 || #en2} VHDL: xcelium> stop -condition {#clk_n == '1'} -if {#enable=='1'|| #reset_n=='1'}
The following command stops the simulation at 5 ns (absolute time). After that, clock changes depending on the condition in the if expression, and this happens repeatedly every 5 ns. The -continue option is used to prevent the simulation from stopping every time the breakpoint triggers. VHDL requires use of the single quotation marks.
xcelium> stop -time 5 ns -start 5 ns
-execute {if {#clk == '0'} {force clk '1'}
else {force clk '0'}} -continue
Process Breakpoints
The following command sets a breakpoint that stops the simulation whenever the process called :load_action is executed.
xcelium> stop -process :load_action
Examples of Other stop Command Modifiers
The following command sequence illustrates the -show modifier. The first command creates a source line breakpoint called break1; the second creates an object breakpoint called break2. The third command shows the status of the two breakpoints.
xcelium> stop -line 12 -name break1
Created stop break1
xcelium> stop -object data -name break2
Created stop break2
xcelium> stop -show
break1 Enabled Line: ./shortdrive.v:12 (scope: top)
break2 Enabled Object top.data
xcelium>
In the following command sequence, breakpoint break1 is first disabled with the -disable modifier and then enabled with the -enable modifier.
xcelium> stop -show
break1 Enabled Line: ./shortdrive.v:12 (scope: top)
break2 Enabled Object top.data
xcelium> stop -disable break1
xcelium> stop -show
break1 Disabled Line: ./shortdrive.v:12 (scope: top)
break2 Enabled Object top.data
xcelium> stop -enable break1
xcelium>
The following command deletes breakpoint break1.
xcelium> stop -delete break1
To disable, enable, or delete the two breakpoints break1 and break2, any of the following commands could be used.
xcelium> stop -delete *1 *2 xcelium> stop -delete break? xcelium> stop -delete br*
The following command displays information on any breakpoint beginning with v or b.
xcelium> stop -show {[vb]*}
Tcl Expressions as Arguments
The stop command has two options that let you specify conditions. Both options require a Tcl expression argument.
-conditionThis option specifies that you are creating a condition breakpoint, as opposed to some other kind of breakpoint, such as a time or object breakpoint. A condition breakpoint triggers when any digital object named in the Tcl expression has an event that would trigger an object breakpoint and the expression evaluates to non-zero, non-x, or non-z. Although condition breakpoints are not triggered by changes in analog objects, you can include analog objects in the conditional expression and their values are used when the condition is evaluated (due to a digital object changing value).
-ifThis option can be used with any breakpoint type, including condition breakpoints. The Tcl expression argument is evaluated, and the stop triggers if the expression evaluates to non-zero, non-x, or non-z.
There are two general rules to keep in mind when writing the Tcl expression:
-
Enclose the expression in braces to suppress immediate substitution of values.
{tcl_expression}If you are using the SimVision environment, these braces are included on the Set Break form.
In the following example, the value of
w[1]would be substituted with its current value (1'bx, for example) if there were no braces. No object would be named in the expression by the time thestopcommand routine sees it, resulting in an error.xcelium> stop -condition #w[1] == 1xcelium> stop -condition {#w[1] == 1}
- You must use either an explicit
valuecommand or the # character to get the object's value into the expression parser because the parser does not understand names. For example, the following command generates an error message.xcelium> stop -time 100 ns -if {r[1] == 1}Use the following commands:Verilog:xcelium> stop -time 100 ns -if {[value r[1]] == 1'b1}xcelium> stop -time 100 ns -if {#r[1] == 1}VHDL:xcelium> stop -time 100 ns -if {[value r(1)] == `1'}xcelium> stop -time 100 ns -if {#r(1) == `1'}
Format specifiers can be used with either the value command or the # sign. If you use the # sign, place the format specifier after the # sign. For example,
Verilog:
xcelium> stop -condition {[value %d out] = 12} xcelium> stop -condition {#%dout = 12}
VHDL:
xcelium> stop -condition {[value %d out] = 12} xcelium> stop -condition {#%dout = 1}
For VHDL, you must enclose vectors in quotation marks and single-bit entities in single quotation marks. For example,
Verilog: xcelium> stop -condition {#clock == 1} VHDL: xcelium> stop -condition {#clock == `1'}
Verilog: xcelium> stop -condition {#count = 4'b0101} VHDL: xcelium> stop -condition {#clock = "0101"}
See the "Basics of Tcl" appendix in Cadence Verilog Simulation User Guide for more details on basic Tcl syntax and on the extensions to Tcl that have been added to handle types and operators of the Verilog and VHDL hardware description languages.
For RNM nets, the following command creates a conditional on-change break when top.rnmnet changes to `wrealXState:
stop -create -object -if {#top.rnmnet = "`wrealXState"} top.rnmnet
