Saving a Configuration as Verilog

The Hierarchy Editor provides the File – Save As Verilog command to save a configuration to a file that can be used with the -file argument of Verilog applications such as xmvlog. The Verilog file can have any name, though it is typically called verilog.f.

The Hierarchy Editor adds a list of Verilog source files to the Verilog file.

For any cellview, if the cellview is a Verilog view (as defined by the master.tag file), then the Verilog source file specified in the master.tag is used. (If the library has a TMP directory associated with it, then the Hierarchy Editor looks for the source file in the temporary directory first, and then, if it is not found, looks for it in the master location.)

If the cellview is not a Verilog view (for example, if it is a schematic), then the Hierarchy Editor determines which Verilog source file to use. If the library has a TMP directory associated with it, the Hierarchy Editor first looks for source files in the temporary directory and then, if it does not find any, looks for them in the master location. If there are multiple source files, then the Hierarchy Editor selects the file according to the following order of precedence (highest to lowest):

verilog.vams
verilog.va
veriloga.va
verilog.v

To save a configuration for Verilog applications,

1. Choose File – Save As Verilog.

The Save As Verilog form appears.

1. Specify the file in which you want to save the configuration:
   1. In the Look in field, select the directory in which you want to save the file.
   2. In the File field, type the name of the file.
      The default value of this field is verilog.f.
2. Click Save.

The Verilog file is saved. If the Hierarchy Editor generated any warnings while creating the Verilog file, it displays a dialog box asking you whether you want to see the warnings.

To save the warnings to a log file,

• Click Write to Message Area.
  The warnings are displayed in the Messages area and also saved in the log file.

Related topics

Save As Form

Save As Verilog Form

Save As VHDL Form

Using the Virtuoso Schematic Editor with the Hierarchy Editor

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