Product Documentation
Virtuoso Design Rule Driven Editing User Guide
Product Version IC23.1, September 2023

3


DRD Support for FinFET Devices

DRD facilitates the creation and placement of FinFET devices that adhere to FinFET-specific spacing, width, and enclosure rules.

This chapter contains the following topics:

For a quick overview of DRD, see DRD for Advanced Node Design.

Defining Discrete Spacing Rules

The allowedSpacingRanges constraint defines a set of legal spacing rules, in the form of ranges and discrete values, between shapes on the same layer or different layers. DRD uses the following parameters of this constraint to support discrete spacing rules for FinFETs:

An example of the technology file definition is shown below:

spacings(
    ( allowedSpacingRanges "Active" 
     'vertical
'stepSize 0.048
'overLayer "FB1"
(">=0.130")
)
) ;spacings

where,

The following figures illustrate this example in DRD Notify mode. As the vertical spacing between the rectangles increases, DRD displays halos and arrows (in yellow) to indicate the incremental legal spacing values.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser assistant, DRD reports an allowedSpacingRanges violation (Marker 1) because the vertical space between the rectangles does not meet the nearest legal spacing value (0.226 user units).

Defining Minimum Spacing Rules

The minSpacing constraint defines the minimum legal spacing between fin boundaries on a layer.

An example of the technology file definition is shown below:

( minSpacing "FB1" 0.130 )

where the fin boundaries are located on layer FB1 and the minimum legal spacing is 0.130 user units.

The following figures illustrate this example in DRD Enforce and Notify modes. DRD displays a halo and an arrow to indicate the minimum legal spacing value between two fin boundaries.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser, DRD reports a minSpacing violation (Marker 1) because the spacing between the fin boundaries does not meet the minimum legal spacing value (0.130 user units).

Defining Directional and Discrete Width Rules

The allowedWidthRanges constraint defines a set of legal width rules, in the form of ranges and discrete values, for shapes on a layer. DRD uses the following parameters of this constraint to support directional discrete width rules for FinFETs:

An example of the technology file definition is shown below:

spacings(
    ( allowedSpacingRanges "Active"
     'measureVertical
'stepSize 0.048
(">=0.062")
)
) ;spacings

where,

The following figures illustrate this example in DRD Notify mode. As the rectangle is stretched vertically, DRD displays arrows to indicate the incremental legal width values.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser, DRD reports an allowedWidthRanges violation (Marker 1) because the vertical dimension of the rectangle does not conform to the nearest legal width value (0.206 user units).

Defining Directional and Discrete PR Boundary Rules

You can define PR boundary rules through the following constraints:

Defining Directional and Discrete PR Boundary Width Rules

The allowedPRBoundaryDimensions constraint defines a set of legal width rules, in the form of ranges and discrete values, for PR boundaries. DRD uses the following parameters of this constraint to support discrete width rules for FinFETs:

An example of the technology file definition is shown below:

spacings(
    ( allowedPRBoundaryDimensions
     'vertical
'stepSize 0.048
(">=0.048")
'ref "prBndry.h"
)
) ;spacings

where,

The following figure illustrates this example in DRD Notify mode. As the PR boundary is stretched vertically, DRD displays arrows to indicate the nearest incremental legal width value.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser, DRD reports an allowedPRBoundaryDimensions violation (Marker 1) because the vertical dimension of the PR boundary does not conform to the nearest legal width value (4.512 user units).

Defining Directional and Discrete PR Boundary Spacing Rules

The minPRBoundaryInteriorHalo constraint defines a set of legal spacing values between a shape on a layer and the surrounding PR boundary. DRD uses the following parameters of this constraint to support discrete spacing rules for FinFETs:

An example of the technology file definition is shown below:

spacings(
    ( minPRBoundaryInteriorHalo "Active"
     'vertical
'stepSize 0.048 0.113
'ref "prBndry.EN"
)
) ;spacings

where,

The following figure illustrates this example in DRD Notify mode. As the vertical spacing between the PR boundary and the enclosed rectangle increases, DRD displays arrows to indicate the incremental legal spacing values.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser, DRD reports a minPRBoundaryInteriorHalo violation (Marker 1) because the vertical spacing between the PR boundary and the enclosed rectangle does not conform to the nearest legal spacing value (1.745 user units).

Snapping Objects to Legal Width Values

You can automatically snap specific objects to the nearest legal width value using discrete dimension gravity. This functionality supports the Create and Stretch commands in Virtuoso for the following objects:

The following figure explains this functionality.

Each legal width value is surrounded by aperture boundaries, which form an aperture zone. An aperture zone is the snap distance between the pointer, or the moving edge of the rectangle, and the legal width value.

As you stretch the rectangle horizontally, the rectangle automatically snaps to legal width A as soon as the pointer enters the aperture zone surrounding legal width A. If you continue to stretch the rectangle, it snaps to legal widths B, and then to C, as soon as the pointer enters their respective aperture zones.

Discrete dimension gravity is turned on by default. To turn off discrete dimension gravity, set the drdEditSmartSnapAllowedWidthSnap environment variable to nil.

Before using discrete dimension gravity, do the following to define the legal width values in your technology file:

Examples of Discrete Dimension Gravity

This functionality is useful while:

Working with Shapes

The following figure illustrates discrete dimension gravity during a single-direction polygon stretch operation:

The following figure illustrates discrete dimension gravity during a two-direction rectangle stretch operation:

Working with Pins

When a pin is created or stretched, it automatically snaps to the nearest legal width value using discrete dimension gravity.

Currently, only rectangular and polygonal pins are supported.

The following figure illustrates how discrete dimension gravity works for pins of type rectangle:

The following figure illustrates how discrete dimension gravity works for pins of type polygon:

Working with Islands

An island is formed when multiple rectangles and polygons on a layer, belonging to the same level of layout hierarchy, overlap or abut. A hierarchical island is formed by shapes on a layer that belong to different hierarchical levels.

The following figure illustrates discrete dimension gravity while stretching a shape in an island of three rectangles.

Discrete dimension gravity works in the same way while creating or stretching shapes in hierarchical islands.

This functionality requires at least one top-level shape in a hierarchical island.

Working with PR Boundaries

The following figures illustrate discrete dimension gravity while working with PR boundaries.

Defining Directional and Discrete Opposite Extension Rules

The minOppExtension constraint defines the total required enclosure between two opposite edges of overlapping shapes on two different layers. DRD uses the following parameters of this constraint to support discrete enclosure rules for FinFETs:

An example of the technology file definition is shown below:

spacings(
    ( minOppExtension "FB1" "Active"
    'vertical
    'stepSizePair (0.048  0) (0.096  0.017)
    )
) ;spacings

where,

The following figures illustrate this example in DRD Notify mode. As the enclosure between the rectangles on FB1 and Active increases vertically and horizontally (to the right), DRD displays arrows to indicate the incremental legal extension values on three sides of the rectangle on layer Active.

The following figure illustrates this example in DRD Post-Edit and Batch-Check modes. As shown in the Annotation Browser, DRD reports a minOppExtension violation (Marker 1) because the vertical enclosure between the rectangles on layers FB1 and Active does not conform to the nearest vertical legal enclosure value (0.192 user units).


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